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Ken became a registered member 3 years, 6 months ago
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Jim Lewis wrote a new post 3 years, 6 months ago
VHDL + Open Source VHDL Verification Methodology (OSVVM) is great for verification and is a competitor to SystemVerilog + UVM. Especially in the FPGA space where VHDL is the dominant language (see the 2020 […]
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Theodoros became a registered member 3 years, 6 months ago
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Juan Carlos became a registered member 3 years, 6 months ago
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Steve replied to the topic OSVVM and Cadence Xcelium in the forum OSVVM 3 years, 7 months ago
Hi Jim,
Thanks for the update! I am now using Xcelium 21.03.007, and the documentation for this version says that OSVVM (utility library only) with tag 2020.12 is pre-packaged. Previously, the documentation referenced tag 2018.04. Also, back in January of this year, I got in contact with a rep at Cadence regarding plans to support all parts of…[Read more]
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Jim Lewis replied to the topic OSVVM and Cadence Xcelium in the forum OSVVM 3 years, 7 months ago
Hi Steve,
A quick update. I am working with Cadence on Xcelium. Things are looking up. I should have more news on this shortly.I have provided them with the full OSVVM regression suite. I am optimistic, but I don’t know the time frame for them to update Xcelium.
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Jim Lewis replied to the topic Synopsys VCS-MX in the forum OSVVM 3 years, 7 months ago
A quick update. I am working with Synopsys on VCS. Things are looking up. I should have more news on this shortly.
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berkan became a registered member 3 years, 7 months ago
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Mariano became a registered member 3 years, 7 months ago
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suleyman became a registered member 3 years, 7 months ago
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Carlos became a registered member 3 years, 7 months ago
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Mohammed became a registered member 3 years, 7 months ago
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