Activity
-
Graeme's profile was updated 3 years, 9 months ago
-
Jim Lewis replied to the topic Compiling UART testbench.pro in Questa in the forum OSVVM 3 years, 9 months ago
Hi Graeme,
You need to dobuild ../UART/testbench/testbench.proIn OSVVM,
buildandincludeuse a path reference relative to the script they are running.
Hence, in testbench.pro, it just saysanalyze TestCtrl_e.vhd. The path to testbench.pro gets
automatically prepended onto the file name. Hence, when writing scripts we only need to know
the…[Read more] -
Graeme started the topic Compiling UART testbench.pro in Questa in the forum OSVVM 3 years, 9 months ago
Have created a sim_dir under OsvvmLibraries_2021_09
Have compiled the osvvv, Common + UART libraries by calling the relevant .pro files
e.g.
build ../UART/UART.proNo probs so far
When I try to execute
build ../UART/testbench/testbench.pro I get this error
####################
####################
do ../UART/testbench/testbench.pro
# vmap…[Read more] -
Jackie Sampsel's profile was updated 3 years, 9 months ago
-
Dave became a registered member 3 years, 9 months ago
-
David became a registered member 3 years, 9 months ago
-
Zach became a registered member 3 years, 9 months ago
-
Ryan became a registered member 3 years, 9 months ago
-
Stephan became a registered member 3 years, 9 months ago
-
monicawilliams became a registered member 3 years, 9 months ago
-
Freddy became a registered member 3 years, 9 months ago
-
Idir's profile was updated 3 years, 9 months ago
-
Tyler became a registered member 3 years, 9 months ago
-
Jim Lewis wrote a new post 3 years, 9 months ago
As the developer of Open Source VHDL Verification Methodology (OSVVM) , I would like to invite the Universal VHDL Verification Methodology (UVVM) community to join us in using and developing OSVVM.
At this […]
-
Palle Nordestgaard changed their profile picture 3 years, 9 months ago
-
Egor became a registered member 3 years, 9 months ago
-
Idir became a registered member 3 years, 9 months ago
-
Ashok became a registered member 3 years, 9 months ago
-
Dominique became a registered member 3 years, 9 months ago
-
Jim Lewis wrote a new post 3 years, 10 months ago
In reply to a LinkedIn post that regurgitated the old statement that VHDL is verbose, I replied, “With the VHDL-2008 update, Verilog is more verbose than VHDL.”
This led my old friend Cliff Cummings and I to […]
- Load More
