Activity
-
Jim Lewis wrote a new post 5 years ago
VHDL-93 (IEEE 1076-1993) created shared variables of an ordinary type as a temporary solution – which was noted in the standard document (aka LRM). VHDL-2000 (IEEE 1076-2000) created protected types as the onl […]
-
Martin became a registered member 5 years ago
-
Kamna became a registered member 5 years ago
-
Koray became a registered member 5 years ago
-
Mathew became a registered member 5 years ago
-
Marine became a registered member 5 years ago
-
Ingo became a registered member 5 years ago
-
Long became a registered member 5 years ago
-
Sabrina became a registered member 5 years ago
-
Miles became a registered member 5 years ago
-
Jim Lewis wrote a new post 5 years ago
Verification components have become an essential part of a structured VHDL environment. In OSVVM we implement verification components as an entity and architecture. This provides RTL engineers with a fam […]
-
Jim Lewis replied to the topic OSVVM and Cadence Xcelium in the forum OSVVM 5 years ago
Hi Steve,
What we find is that users have more influence over vendors than I do. To be fair to them though, OSVVM has had numerous updates through COVID. One benefit of teaching on-line and not traveling is that I have had more time to work on OSVVM.One of my goals is to get the OSVVM compile scripts working under Cadence Xcelium. If you…[Read more]
-
Arminmt became a registered member 5 years ago
-
Terje became a registered member 5 years, 1 month ago
-
Gert Baumfacher became a registered member 5 years, 1 month ago
-
Steve started the topic OSVVM and Cadence Xcelium in the forum OSVVM 5 years, 1 month ago
Hi everyone,
It is my understanding that OSVVM release 2018.4 is pre-packaged with Cadence Xcelium version 20.03. Does anyone know if/when newer/latest release(s) will be pre-packaged with Xcelium?
Thanks!
-
MOHAMMED became a registered member 5 years, 1 month ago
-
Miroslav Marinkovic replied to the topic AlertLogPkg (OSVVM 2020.08) in the forum OSVVM 5 years, 1 month ago
Hi Stefen,
Regarding topic 2) I think there is a problem with that specific version Questa/ModelSim 2019.2, but I don´t know exactly a reason.
Try another version (previous or later).Best,
Miroslav -
RuslantgoQF became a registered member 5 years, 1 month ago
-
Jim Lewis wrote a new post 5 years, 1 month ago
The OSVVM 2020.10 release is finally out.
Why 2020.10?
Yes I realize it is now late November. So why 2020.10? In late October, the code was done and marked as 2020.10 with the expectation that the […]
-
One of the main things what OSVVM models differentiate from other available solutions is the extensive documentation. I like that very much.
I remember closed source models which only have very little documentation and second, were written very poor. I used an FPGA-vendors eMMC model some years ago which was created in addition to the MMC controller unit we use. The model was only very basic and without doc, only the controller had some basic docs. After digging through the (Verilog) code I added some fundamental things like an associative array to allow data write/read checks coverage and assertions. Even with my little knowledge of (System) Verilog I was able to do that better.
-
- Load More
