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Jim Lewis wrote a new post 5 years, 4 months ago
I will be in Europe in March doing presentations on Open Source VHDL Verification Methodology (OSVVM) at the 2nd Workshop on Open-Source Design Automation (OSDA) and at the 5th Space FPGA Users Workshop […]
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Jim Lewis replied to the topic Intelligent Coverage Random test generation in the forum OSVVM 5 years, 4 months ago
Hi Ken,
Yes and no. SV does not have this built into it or the UVM library.OTOH, Accellera created a language that layers on top of other languages (I think VHDL too), called PSS (Portable Test and Stimulus Standard). Of course, it adds another layer of $$$$$ to your simulator budget.
Best Regards,
Jim -
Cahit's profile was updated 5 years, 4 months ago
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