OSVVM: Making VHDL Transaction Based Testbenches Simple, Readable, Powerful, and Fun
Just because your design is complex does not mean your testbench needs to be. In OSVVM we have found that with proper abstractions we can create simple, readable, and powerful testbenches.
In OSVVM 2016.11 we released the transaction based modeling approach we have been using for the past 20 years in our verification practice and classes. Looking at its block diagram, you will notice that its architecture looks similar to SystemVerilog + UVM.
Just like SystemVerilog, the OSVVM approach has a top-level sequencer, here named TestCtrl; it has verification models, CpuModel, UartTx, UartRx, and Memory; it has a top level testbench, sometimes called a test harness, named TbMemIO; and finally it has connections between the test sequencer and the models which we implement with OSVVM interfaces.
All of the models (TestCtrl, CpuModel, UartTx, UartRx) in the OSVVM environment are typically implemented with an entity and architecture. The coding of these models can be either behavioral or RTL-like. Generally this means that the models written by the testbench team are easily read by the RTL design team. It also means the RTL team can write testbench models.
An architecture of the top-level sequencer, TestCtrl, typically captures one test of the test suite. This allows the entire test to be viewed in one place. This is accomplished by using a separate process to sequence each interface of the DUT and utilizing OSVVM synchronization primitives (released in 2016.11) to coordinate activities in separate processes when necessary.
The final piece of the puzzle is OSVVM interfaces. An OSVVM Interface connects TestCtrl to a transaction based model. Each model has it own separate connection to TestCtrl. Since an OSVVM Interface is inout of both models, it is created using a record whose elements use the resolution function resolved_max from the OSVVM package ResolutionPkg. Using OSVVM Interfaces provides a simple migration path to VHDL-2017 Interfaces.
Just like SystemVerilog + UVM, OSVVM offers a complete VHDL verification methodology from transaction based testbenches, to functional coverage and randomized test generation, to scoreboards and memory modeling, to error reporting and verbosity control, and to basic utilities (process synchronization).
Ready to go the next step in your VHDL testbenches? Join me at one of the upcoming Advanced VHDL Testbenches and Verification classes. This class is a 5 day investment in time. Expect to gain deep knowledge in the application of OSVVM to ASIC and FPGA verification.
|June 12 – 16 and June 26 – 29||on-line||Enroll with SynthWorks|
|May 30 -June 2 and June 12-16||Web Class||Enroll with SynthWorks|
|July 17-21||Freiburg, Germany||Enroll with PLC2|
|July 31 – Aug 4 and Aug 14 – 18||on-line||Enroll with SynthWorks|
|Aug 28 – Sept 1 and Sept 11 – 15||on-line||Enroll with SynthWorks|
|September 25 – 29||Copenhagen, DK||Enroll with FirstEDA|
For our complete schedule see: https://synthworks.com/public_vhdl_courses.htm
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