OSVVM at OSDA and ESA’s SEFUW

I will be in Europe in March doing presentations on Open Source VHDL Verification Methodology (OSVVM) at the 2nd Workshop on Open-Source Design Automation (OSDA) and at the 5th Space FPGA Users Workshop (SEFUW).

OSDA,  Friday March 13

First stop is Grenoble, France.   I will be presenting an hour long talk on OSVVM on Friday March 13 at OSDA which is held in conjunction with Design, Automation, and Test in Europe (DATE).   I am excited to be going back to Grenoble.   I lived there for 6 months back in 1993.

ESA’s SEFUW,  Tuesday March 17

The next stop is Noordwijk, The Netherlands.  On Tuesday March 17 I will be presenting, “Getting Started with OSVVM, VHDL’s #1 Verification Methodology” at SEFUW.    I am excited to see ESA and connect with the European Space community.

On-Site Class?

Looking to improve your VHDL verification methodology?   OSVVM provides a complete solution for VHDL FPGA or ASIC verification.  It facilitates the creation of a powerful, concise, and readable test environment.  Each piece can be used separately.  Hence, you can learn and adopt pieces as you need them.  There is no new language to learn.

I am in Europe several times a year.   Contact me (jim@synthworks.com) if you would like to schedule an on-site OSVVM class.

Meet Up in Grenoble or Noordwijk?

If you are in Grenoble or Noordwijk send me a note if you would like to meet up.