Announcing OSVVM 2020.07: AXI4 + Model Independent Transactions
Up your VHDL verification game with the latest from Open Source VHDL Verification Methodology (OSVVM).
OSVVM 2020.07 focuses on Verification Components. AXI4 Full models were added. Axi4Lite, AxiStream, and UART models were updated to use the new OSVVM Model Independent Transactions.
AXI4 (and Axi4Lite) verification components are the most challenging and most interesting I have worked on. One of the challenges of the AXI interface is due to read and write transactions being handled by independent Write Address, Write Data, Write Response, Read Address, and Read Data interfaces. The AXI interface supports transactions of the following forms.
An AXI write transfer can be of the form where write address and write data occur on the same cycle, as shown for A1 and D1. However, the write response, R1, will not occur until at least a cycle later. Simultaneous to receiving a write response, new write addresses (and write data) can be dispatched in a pipelined fashion as shown for A2, A3, and A4. This is one of the brilliant things about AXI transfers – no wasted bus cycles.
Transfers can also be of the form where write data follows write address by one or more clock cycles, as shown for A5 and D5. Again, A6 and A7 follow A5 in a pipelined fashion. Alternately an AXI responder may receive write data before write address (most likely due to interconnect delays) as shown for A8 and D8.
Now consider that Read Address and Read Data may occur at any time in relationship to write – including simultaneously with a write operation.
Hence, to support and verify the full capability of an AXI Interface, a verification component needs to support independent (aka concurrent or multi-threaded) execution of the Write Address, Write Data, Write Response, Read Address, and Read Data interfaces. At the same time, it also needs to correlate aspects of the same transaction (such as a write). Sometimes the verification component will need to block until a transaction completes and sometimes not. Sometimes the write address will need to be dispatched independently from the write data (to introduce a skew between them) and then optionally queue the next set of transactions without waiting.
An interesting model indeed. Unfortunately, most open source verification components fall short and do not support independent execution of the AXI interfaces. Currently the OSVVM AXI4 and Axi4Lite verification components are the only open source VHDL verification components with this capability.
I am excited about the direction that OSVVM Model Independent Transactions have evolved. The intent of Model Independent Transactions is that all address bus interfaces (AXI4, Avalon, Wishbone) support the same set of transactions and, similarly, that all streaming interfaces (UART, AxiStream, …) support the same set of transactions. The intent is to increase the reuse of test cases (in the test sequencer) and reduce the work of developing verification components. I will continue with these thoughts in a future post.
There is extensive documentation on the OSVVM utility library in the documentation repository.
On the other hand, formal documentation for the verification components is a work in progress. For now, there are two presentations and the testbenches.
- Creating an AXI4 Lite, Transaction Based VHDL Testbench with OSVVM
- Creating Better Self-Checking FPGA Verification Tests with Open Source VHDL Verification Methodology (OSVVM)
- A great way to learn OSVVM Verification Components is to run the testbenches and then read the test cases (see next section)
Getting and Running the testbenches
The OsvvmLibraries repository contains all other OSVVM repositories as a submodule. Hence, when you get OsvvmLibraries, you get everything you need. You can get OsvvmLibraries by calling git clone with the “–recursive” option:
$ git clone --recursive https://github.com/osvvm/OsvvmLibraries
A zip file is available at osvvm.org/downloads.
Once you have OsvvmLibraries, you can compile all of the OSVVM libraries by following the directions in the OSVVM-Scripts repository.
What’s Next In OSVVM?
First let me open it up to you. In the comments, let us know what you would like to see next. What verification components do you need? What extensions in the utility library would you like to see?
Want to help adding features and/or verification components to OSVVM? Join us. See the next section for details.
In the verification component library, we have additional extensions planned for the AXI verification components. In the utility library, we are creating a unified specification tracking capability that is an integral part of AlertLogPkg. In the scripting library, we are transitioning the tool abstraction capability to using procedures rather than variables as an abstraction method (see the dev branch).
OSVVM + IEEE Open Source project.
OSVVM is now an IEEE Open Source project. Join us in further developing OSVVM. More details about participating are in my OSVVM Call for Participation blog post and the contributing guidelines are in OsvvmLibraries/CONTRUBUTING.md.
Don’t let the IEEE login intimidate you, you get that for free (ie: no membership required) – just like at GitHub.
Open Source VHDL Verification Methodology (OSVVM) is a methodology and libraries that simplify the creation of structured testbenches that are readable and powerful. OSVVM supports the same capabilities that other verification languages (such as SystemVerilog + UVM) support – from a structured testbench framework using transaction level modeling, to functional coverage and randomized test generation, to scoreboards and FIFOs, to error handling utilities, to synchronization utilities, to memory modeling, and to verification components – All you need is OSVVM.
OSVVM verification components are a growing set of open source verification components. They now include:
- AXI4 Master – supports single word and burst transfers dispatched by test sequencer
- AXI4 Memory – supports single word and burst access to an internal memory
- AXI4 Lite Responder – supports single word transfers dispatched by test sequencer
- AXI4 Lite Master
- AXI4 Lite Memory
- AXI4 Lite Responder
- AXI Stream Transmitter
- AXI Stream Receiver
- UART Transmitter (with error injection)
- UART Receiver (with error injection)
Testbenches for each model are in the Git repository, so you can run a simulation and see a live example of how to use the models.
Getting Started with OSVVM