Addressing VHDL Verification Challenges with OSVVM
Most people don’t think of VHDL as a verification language. However, with the Open Source VHDL Verification Methodology (OSVVM) utility and verification component libraries it is. Using OSVVM we can create readable, powerful, and concise VHDL verification environments (testbenches) whose capabilities are similar to other verification languages, such as SystemVerilog and UVM.
This article covers the basics of using OSVVM’s transaction-based test approach to write directed tests, write constrained random tests, use OSVVM’s generic scoreboard, add functional coverage, add protocol and parameter checks, add message filtering, and add test wide reporting.
WHY VHDL? WHY OSVVM?
According the 2018 Wilson Research Group Functional Verification Study:
- 62% of FPGA designs worldwide use VHDL
- 17% of FPGA verification projects worldwide use OSVVM (or 38% of VHDL FPGA verification projects)
- For Europe, 30% of FPGA verification projects use OSVVM while only 20% use UVM
This makes OSVVM the #1 VHDL FPGA verification methodology worldwide and the #1 FPGA verification methodology in Europe.
BENEFITS OF OSVVM . . .
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GETTING AND RUNNING OSVVM (the 2020.07 Update)
We have been busy updating OSVVM. With the 2020.07 Update, we made everything OSVVM available in a single repository on GitHub at https://github.com/OSVVM. Retrieve it using git as shown below.
git clone --recursive https://github.com/OSVVM/OsvvmLibraries.git
Alternately you can get the release from the OSVVM.org download page. Note that you will need to register to use the download link – however it is a zip file and if you are not friends with git you may find you like this method better.
The Axi4 (full), Axi4Lite, AxiStream, and UART verification components come with OSVVM style testbenches. Start your simulator and follow the steps below to run the AxiStream verification component.
Complete directions for running the scripts are in OsvvmLibraries/Scripts/README.md. Note the 2020.08 version (available shortly) adds scripting support for ActiveHDL.
The tests for the UART and AXI4Lite verification components are run in the same manner.
OSVVM goes well beyond the basics shown in this article. To learn more, see the documentation on the GitHub site, or take SynthWorks’ Advanced VHDL Testbenches and Verification class. We have been offering our classes on-line for 7 years now and are good at it. We are currently offering classes at least once a month, see our schedule for more details.