OSVVM Model Independent Transactions
OSVVM Model Independent Transactions
I take great joy in reuse – this is true whether it is a plastic bag or VHDL code. OSVVM Model Independent Transactions were added in the 2020.07 release and are directed at improving reuse – and hence bring me great joy.
Model Independent Transactions provide two aspects of reuse. First, they simplify verification component development by reducing the number of steps. Second, they simplify reuse of test cases between similar models since each Address Bus Interface (AXI, Avalon, …) and each Streaming Interface (UART, AxiStream, …) share a common set of model independent transactions.
First, What is a Transaction?
A transaction is an abstract representation of an interface operation or verification component directive. An interface operation could be a write or a read on an address bus interface. A verification component directive is either a query, such as get a count of transactions executed on the interface (GetTransactionCount) or an action, such as wait for one clock cycle relative to the verification component (WaitForClock).
In OSVVM, transactions are implemented with a procedure call. More on this in a minute.
The OSVVM Testbench
OSVVM uses the same architecture used by most modern methodologies. You might notice the similarity between this and SystemVerilog’s testbench architecture.
A basic OSVVM Testbench consists of a test sequencer (called TestCtrl), a verification component, and an instance of the design under test (DUT). As the design complexity increases, we add a separate verification component for each interface in the DUT and we add additional processes to the test sequencer.
The test sequencer calls the transaction procedures to hand off transaction information to the verification component. In general, it has a separate process for each independent interface. Writing a test is simply a set of calls to the transaction procedures in the process dedicated to the interface:
Write(AxiInitiatorRec, REG1_ADDR, X"AAAA") ;
Read (AxiInitiatorRec, REG1_ADDR, rData) ;
AffirmIfEqual(rData, X"AAAA", "Write, Read of REG1_ADDR");
OSVVM’s verification components are entities and architectures – meaning we create structure the same way as done in RTL designs. If you want to work harder and use cool language features like OO, then you might consider SystemVerilog. On the other hand, we don’t need a software like OO approach to create models in VHDL – we simply create them the same way used for RTL design. This means your RTL designers can both read the testbench and write tests. While it is good to have independent design and verification teams, we need to be able to move team members around on a project by project basis – with OSVVM, this is an option.
Simplifying Verification Component Development
OSVVM verification components have 3 elements to them: a transaction interface, transaction initiation procedures, and the entity/architecture that implements the verification component.
The job of a verification component is to implement the specifics of the interface behavior – ie: the signal wiggling to the design under test (DUT).
The transaction interface is used by the test sequencer to provide transaction information to the verification component. OSVVM implements the transaction interface as a record. This is explored in further detail in my article “VHDL Interfaces: VHDL-2019 & OSVVM” – the article includes what we do now as well as the simplifications provided by VHDL-2019.
The transaction initiation procedures are called by the test sequencer to create tests. Their main task is to put the information passed to them into the transaction interface. For example, for an Address Bus write transaction, the procedure needs to pass the operation type (write), the write address, and the write data to the verification component. For a WaitForClock, the procedure needs to pass the operation type (WaitForClock) and the number of clock cycles to wait. The procedures use OSVVM defined handshaking methods to signal to the model that a new transaction is available.
OSVVM Model Independent Transactions provide us with a short cut. They define the transaction interface (the record) and the transaction initiation procedures. Hence, we can focus on just the verification component – skipping the tedious stuff – this is reuse at its best. This is particularly important since multi-threaded interfaces like AXI are challenging enough already.
OSVVM Model Independent Transactions are defined for Address Bus Interfaces (such as AXI, Avalon, …) and Streaming Interfaces (such as UART, AxiStream, …).
Simplifying Test Case Reuse
OSVVM Model Independent Transactions simplify the reuse of test cases between similar models since each Address bus Interface (AXI, Avalon, …) and each Streaming Interface (UART, AxiStream, …) share a common set of model independent transactions.
All test cases are written in terms of these transactions. Hence, if we have to switch between an AXI interface and an Avalon interface, in general, we do not have to re-write the test cases – we simply have to replace the design IP and the verification components and re-run the old tests.
On the other hand, if we use another methodology that uses design specific naming (such as AxiBusWrite, AxiBusRead, …) and the interface changes (from AXI to Avalon), then we have to edit all of the test cases.
As another example, if you have written a procedure that sends ethernet packets over an AxiStream interface, you can use that same procedure to send ethernet packets over a UART.
Open Source VHDL Verification Methodology (OSVVM) is a methodology and libraries that simplify the creation of structured testbenches that are readable and powerful. OSVVM supports the same capabilities that other verification languages (such as SystemVerilog + UVM) support – from a structured testbench framework using transaction level modeling, to functional coverage and randomized test generation, to scoreboards and FIFOs, to error handling utilities, to synchronization utilities, to memory modeling, and to verification components – All you need is OSVVM.
OSVVM verification components are a growing set of open source verification components. They now include:
- AXI4 Master – supports single word and burst transfers
- AXI4 Memory – supports single word and burst access to an internal memory
- AXI4 Lite Responder – supports single word transfers
- AXI4 Lite Master
- AXI4 Lite Memory
- AXI4 Lite Responder
- AXI Stream Transmitter
- AXI Stream Receiver
- UART Transmitter (with error injection)
- UART Receiver (with error injection)
Testbenches and OSVVM simulation scripts for each model are in the Git repository, so you can run a simulation and see a live example of how to use the models (directions are below).
There is extensive documentation on the OSVVM utility library in the documentation repository (https://github.com/OSVVM/Documentation). This includes the Address_Bus_Model_Independent_Transactions_user_guide.pdf and the Stream_Model_Independent_Transactions_user_guide.pdf.
On the other hand, formal documentation for the verification components is a work in progress. For now, you can learn about OSVVM verification components by seeing the following two presentations and by running testbenches.
- Creating an AXI4 Lite, Transaction Based VHDL Testbench with OSVVM
- Creating Better Self-Checking FPGA Verification Tests with Open Source VHDL Verification Methodology (OSVVM)
- A great way to learn OSVVM Verification Components is to run the testbenches and then review the test cases (see next section)
Getting and Running the testbenches
The OsvvmLibraries repository contains all other OSVVM repositories as a submodule. Hence, when you get OsvvmLibraries, you get everything you need. You can get OsvvmLibraries by calling git clone with the “–recursive” option:
$ git clone –recursive https://github.com/osvvm/OsvvmLibraries
A zip file is available at https://osvvm.org/downloads.
Once you have OsvvmLibraries, follow the steps in the OsvvmLibraries/Scripts/README.md (also at https://github.com/OSVVM/OSVVM-Scripts/) to compile the verification components and run the simulations.
What Would You Like Next In OSVVM?
In the comments, let us know what you would like to see next. What verification components do you need? What extensions in the utility library would you like to see?
Want to help adding features and/or verification components to OSVVM? Join us. See the next section for details.
OSVVM + IEEE Open Source project.
OSVVM is now an IEEE Open Source project. Join us in further developing OSVVM. More details about participating are in my OSVVM Call for Participation blog post and the contributing guidelines are in OsvvmLibraries/CONTRUBUTING.md.
Don’t let the IEEE login intimidate you, you get that for free (ie: no membership required) – just like at GitHub.
Getting Started with OSVVM
The fastest way to get started with OSVVM is SynthWorks’ Advanced VHDL Testbenches and Verification which is available world wide either on-line or on-site (once we can travel again). Here is our current class schedule. During the pandemic we are offering on-line classes monthly.
OSVVM is free, open source software. With this changing world, we are looking for funding sources for OSVVM. If you know of any organizations who can support our work, please reach out to me.