Guest Blog: OSVVM with Verilog Vendor Models by Timothy Stotts
Hi,
My name is Timothy Stotts, an FPGA and Embedded Systems engineer in upstate New York. There is an often less-discussed technique of adding vendor models to the VHDL test-bench for verifying the peripheral driver and functional behavior of your FPGA design. A quick search on Google shows little documentation on adding IC vendor models to a VHDL test-bench. And during my work experience, the topic rarely came up. As an example of adding these models, I would like to discuss my recent success at adding a Serial NOR Flash model to a VHDL test-bench, allowing data to be written to and read from an external Flash peripheral over SPI bus, during the mixed-language simulation of a VHDL design that exercises the NOR Flash.
To start with, let’s consider an FPGA design that erase/program/reads/compares data to a Micron N25Q NOR Flash in Extended SPI mode. The design is a basic VHDL RTL design with a bus connection to the Serial NOR Flash. The purpose of the design is to perform a pattern-based memory test on the NOR Flash. To check the design in a simulator, such as Riviera-PRO, a testbench must be added. An OSVVM test-bench was added to the VHDL project. Note that Extended SPI would be simple to add to the test-bench for interfacing with the Serial NOR FLash ports of the FPGA design; however, the Serial NOR Flash is a complex device with many modes of operation, taking many commands and presenting status registers. Thus, it would be complex to create a behavioral model of the peripheral. A quick search on micron.com reveals that Micron provides a behavioral Verilog model of their N25Q serial NOR flash memory chip. The concern here is how can we incorporate this Verilog model into the OSVVM test-bench. This would allow us to not author a rudimentary NOR Flash model ourselves.
For the mentioned design, the N25Q256A Mbit NOR Flash resides on a PCB produced by Digilent Inc. The unit is called Pmod SF3. Here I create a VHDL entity and architecture for instantiating the Pmod SF3 inside of the VHDL test-bench. The code for this model looks similar to the following.
entity tbc_pmod_sf3 is port( ci_sck : in std_logic; ci_csn : in std_logic; cio_copi : inout std_logic; cio_cipo : inout std_logic; cio_wrpn : inout std_logic; cio_hldn : inout std_logic ); end entity tbc_pmod_sf3; architecture simulation_default of tbc_pmod_sf3 is component N25Qxxx_wrapper is port( S : in std_logic; C : in std_logic; HOLD_DQ3 : inout std_logic; DQ0 : inout std_logic; DQ1 : inout std_logic; W_DQ2 : inout std_logic); end component N25Qxxx_wrapper; -- more logic begin -- more logic u_N25Qxxx_wrapper : N25Qxxx_wrapper port map( S => ci_csn, C => ci_sck, HOLD_DQ3 => cio_hldn, DQ0 => cio_copi, DQ1 => cio_cipo, W_DQ2 => cio_wrpn ); end architecture simulation_default;
Note from this example two important design techniques. First, the unit is an entity/architecture pair in VHDL. This allows us to later create additional architecture definitions, should we decided to instantiate different logic, configurable at the VHDL Configuration Test Definition; thus, having two tests that differ in their definition of the innards of the Pmod SF3 model. Second, a Verilog wrapper for the N25Q NOR Flash model is instantiated with the Pmod SF3 architecture. To accomplish this–the flash model is Verilog, not VHDL–it is necessary to define the component in the architecture preamble and define the port-mapped instance in the architecture body. Note that DQ0, DQ1, DQ2, DQ3, are all defined as `inout` as the flash model is capable of Extended SPI, Dual SPI, Quad SPI. Note that to my knowledge, the instantiation should not use `u_N25Qxxx_wrapper : entity work.N25Qxxx_wrapper` to instantiate the model, but uses the component/instance pair instead.
The purpose behind the Verilog wrapper may not be immediately obvious; but let me show the RTL here.
`timescale 1ns / 1ps
module N25Qxxx_wrapper(
S, C, HOLD_DQ3, DQ0, DQ1, W_DQ2
);
parameter time powerup_time = 150e0;
input S;
input C;
inout HOLD_DQ3;
inout DQ0;
inout DQ1;
inout W_DQ2;
`define VoltageRange 31:0
reg [`VoltageRange] Vcc;
wire RESET2;
assign RESET2 = 1'b1;
initial
begin
Vcc = 'd3300;
#(powerup_time+100);
end
N25Qxxx #() u_N25Qxxx (
.S(S),
.C_(C),
.HOLD_DQ3(HOLD_DQ3),
.DQ0(DQ0),
.DQ1(DQ1),
.Vcc(Vcc),
.Vpp_W_DQ2(W_DQ2),
.RESET2(RESET2)
);
endmodule
Here, in the wrapper, we can see how the NOR Flash Verilog model is instantiated and powered-on upon simulation start. The clock signal `C_` is mapped to the VHDL-friendly signal name `C`. The `Vcc` signal is a fixed-point representation of the VCC power level, and is 3.3 V DC on the Pmod SF3 schematic. The signal `RESET2` is mapped to a constant pull-up to value of `1`, which also matches the Pmod SF3 schematic if that output pin is not mapped in the FPGA design.
Now the Pmod SF3 model is complete and can be added to the test-bench (component declaration not shown).
-- Simulate the Pmod ACL2 peripheral u_tbc_pmod_sf3 : tbc_pmod_sf3 port map( ci_sck => so_pmod_sf3_sck, ci_csn => so_pmod_sf3_csn, cio_copi => sio_pmod_sf3_copi, cio_cipo => sio_pmod_sf3_cipo, cio_wrpn => sio_pmod_sf3_wrpn, cio_hldn => sio_pmod_sf3_hldn );
If you run this in the simulator, the Pmod SF3 test-bench component will now simulate the peripheral’s NOR Flash with a model from the IC vendor, instead of a custom in-house model. Note that different vendors have different licenses on their IC Verilog models; and it may not be appropriate to use the IC Verilog model in a commercial setting; it may not be appropriate to distribute the model with the test-bench; and it may not be appropriate to discuss the model on-line. These considerations are addressed in the model’s license.
There are more considerations for this design, including simulator argument options, and N25Q model timing parameters, which are discussed at:
“Mixed language test-bench of fpga-serial-mem-tester-1 VHDL-only RTL“,
and
Test-bench simulation setup with Riviera-PRO, HOWTO.`
————–
A quick note from Jim. Looking for an experienced VHDL verification engineer Make sure to note that Timothy’s Linkedin page says: Seeking part-time engineering work in Rochester, NY, or Finger Lakes, NY; or part-time Work From Home (WFH). Currently engaged in employment hunt. #opentowork