Announcing OSVVM Release 2022.02
Improve your verification capabilities with Open Source VHDL Verification Methodology (OSVVM).
OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC.
Release 2022.02 continues our focus on test reporting and adds:
- Log (transcript) files can now be html as well as text (log).
- Link to html transcript file now included in test detailed reports to quickly find the simulation output of each test.
- Scoreboard reports are now included in the test detailed reports
- Scripts optionally activate code coverage and simplify code coverage collection, merging, and reporting (html).
- Code coverage reports, when generated, are linked into the OSVVM html build reports.
Getting the OSVVM Release
You can find the OSVVM release on OSVVM.org as a zip file at the OSVVM Downloads Page.
The library is also available on GitHub in the OsvvmLibraries Repositories.
Download the entire OSVVM library using git clone with the “–recursive” flag:
$ git clone --recursive https://github.com/osvvm/OsvvmLibraries
Give Us A Star on GitHub
GitHub ranks projects based on the number of stars given by the community.
Even if you are downloading OSVVM releases here on OSVVM.org, please be sure to
give us a star on GitHub at both the OSVVM repository and
Getting Started with OSVVM
OSVVM has a complete set of documentation. You will find it at the OSVVM Documentation Repository. The readme at the bottom of this page provides a reading list for the documentation.
The fastest way to learn OSVVM is SynthWorks’ Advanced VHDL Testbenches and Verification which is available world wide either on-line or on-site (once we can travel again). Here is our current class schedule. The next class dates are:
- March 14 – 25
- April 11 – 22
- May 16 – 27
Our on-line class session is offered as 10 half-day sessions. The lecture sessions are approximately 2.5 hours long. Please allow up to 3 hours in your planning in the event of overrun. Independent exercises and labs will take about 1.5 to 2.5 hours per day and are supported by phone, email, or web sessions as necessary. More details on our on-line sessions are at SynthWorks On-line VHDL Class Details.