OSVVM Events
Upcoming OSVVM conference/webinar and training classes:
| September 14 | OSVVM in a NutShell, VHDL’s #1 Verification Methodology at Verification Futures Conference Austin, TX in-person and On-line |
| September 18 – 29 |
On-line Class Session: Advanced VHDL Testbenches and Verification – OSVVM Bootcamp |
| October 16 – 20 |
In-person Class Session in Bracknell, UK: Advanced VHDL Testbenches and Verification – OSVVM Bootcamp |
| Oct 23 – Nov 3 |
Available for on-site class in Europe. |
| November 6 – 17 |
On-line Class Session: Advanced VHDL Testbenches and Verification – OSVVM Bootcamp |
| December 4 – 15 |
On-line Class Session: Advanced VHDL Testbenches and Verification – OSVVM Bootcamp |
Verification Futures Conference Austin, TX
Join myself and 800+ other attendees at this hardware design verification focused in-person and on-line conference.
I will be presenting, OSVVM in a NutShell, VHDL’s #1 Verification Methodology.
If you are using VHDL for design, OSVVM brings you
- A structured transaction-based verification framework using verification components
- A common, shared transaction API for address bus (AXI4, Avalon, …) and streaming (AXI Stream, UART) verification components
- Improved readability and reviewability by the whole team including software and system engineers.
- Improved reuse and reduced project schedules.
- Buzz word features including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering that are simple to use and work like built-in language features.
- A common scripting API to run all simulators. OSVVM scripting supports GHDL, NVC, Aldec Riviera-PRO and ActiveHDL, Siemens Questa and ModelSim, Synopsys VCS, and Cadence Xcelium.
- A Co-simulation capability that supports running software (C++) in a hardware simulation environment.
- Unmatched test reporting with HTML based test suite reports, test case reports, and logs that facilitate debug and test artifact collection.
- Support for continuous integration (CI/CD) with JUnit XML test suite reporting.
- A rival to the verification capabilities of SystemVerilog + UVM.
If you are in Austin and are already using OSVVM, stop by before my presentation and we can talk about OSVVM, what is coming up in OSVVM, or what you would like to see coming up in OSVVM.
On-line Class Sessions: Advanced VHDL Testbenches and Verification
In Advanced VHDL Testbenches and Verification – OSVVM Bootcamp class you will learn the latest VHDL verification techniques including transaction based modeling (aka verification components), self-checking, error reporting (alerts and affirmations), message filtering (logs), scoreboards, memory modeling, functional coverage, directed, algorithmic, constrained random, and Intelligent Coverage random test generation. Create an OSVVM VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog or ‘e’. Our techniques work on VHDL simulators without additional licenses and are accessible to RTL engineers.
If you are just getting started with VHDL, we also offer our Comprehensive VHDL Introduction and VHDL Coding for Synthesis classes during these time periods.
On-line sessions of this class allow us to provide a slower paced offering than our in-person sessions.
In-person Class Session in Bracknell, UK: Advanced VHDL Testbenches and Verification
Join me on October 16 – 20 in Bracknell, UK for an in-person session of Advanced VHDL Testbenches and Verification – OSVVM Bootcamp.
Available for on-site class in Europe
I will be on travel in Europe on the weeks of October 23 to November 3. If you are looking for an on-site session of Advanced VHDL Testbenches and Verification (5 days) or Essential VHDL Testbenches and Verification (3 days), be sure to reach out to me at jim at synthworks.com.