Why no constraint solver? Are you going to add one? Jim Lewis December 7, 2012 Functional Coverage, OS-VVM in general, Randomization 1 Related Posts Are random number generators really random? Why Functional Coverage? The myth of ‘randc’ randc in OSVVM – another view 1 Comment Jerry Kaczynski December 14, 2012, 09:52 Log in to Reply Let me chime in with one more reason not to implement constraint solver: speed. Constraint solvers implemented in SystemVerilog tools are slowing down the simulation (and they are pieces of binary code!). Any attempt of implementing solver in VHDL package would have to be even slower and would not bring any significant benefits. And one more piece of information: people do not know how to write efficient constraints. When I polled a couple of friends working in tech support, they have provided examples of simulator users’ constraints so ridiculous that you start to wonder how those guys manage to keep their jobs (<evil grin>). Intelligent Coverage is, well, more intelligent than solvers – i.e. does not rely on end-users knowing all rules… Leave a Reply Cancel ReplyYou must be logged in to post a comment.