Upcoming OSVVM conference/webinar and training classes: September 14 OSVVM in a NutShell, VHDL’s #1 Verification Methodology at Verification Futures Conference Austin, TX in-person and On-line September 18 – 29 On-line Class Session: Advanced VHDL Testbenches and Verification – OSVVM Bootcamp October 16 – 20 In-person Class Session in Bracknell, UK: Advanced VHDL Testbenches and ... »
OSVVM release 2023.07 updates OSVVM’s Requirement Tracking (aka Specification Tracking) capability so that HTML and CSV based merged requirements reports are produced automatically. Requirements Tracking (Part 1) started with the 2020.08 release. In the 2020.08 release, each test could write out a CSV requirements report. The expectation was that external requirements tools imported these and merg... »
Summary of 2023.07 Changes AlertLogPkg: Added WriteRequirementsYaml to write requirements for a test case into a YAML file ReportPkg: In EndOfTestReports if GotRequirements it calls WriteRequirementsYaml. Hence saving requirements is automatic. Scripts: For each test suite, merges the requirements yaml files for each test case and produces a test suite requirements HTML Scripts: For each bu... »
Summary of 2023.05 Changes Co-simulation updates Added split transaction methods for address bus model independent manager Added support address bus model independent subordinate/responder Added support for streaming bus model independent transactions Added test data pattern generation methods Added data check methods AxiStreamTransmitter and AxiStreamReceiver VC: Randomize delays for TVali... »
Summary of 2023.04 Changes Updated co-simulation environment to support both Streaming Interfaces as well as Address Bus Interfaces. More details in a future post by Simon Script settings are now split between OsvvmScriptSettings.vhd which has deferred constants and a generated package body OsvvmScriptSettings_Generated.vhd (which is in the .gitignore) – Thanks Philip Updated Interrup... »
By Simon Southwell, OSVVM CoSim Technical Lead Introduction I have written previously about co-simulation in my series of LinkedIn articles about using the programming interfaces of logic simulator tools in a fairly generic way, summarising the possibilities and referencing, in outline, some real-world use cases. Since then, I have been collaborating to bring some of these co-simulation features t... »
Summary of 2023.01 Changes Co-simulation environment that supports running software (C++) in a hardware simulation environment. Added OsvvmScriptSettings.vhd to the OSVVM utility library. Autogenerated when the OSVVM library is analyzed. Script settings with the OSVVM library Added Interrupt generator and updated interrupt handling. Added PassThru VC for Axi4, Axi4Lite, and AxiStream to act... »
Summary of 2022.12 Changes Updated StartUp.tcl to use OSVVM_TOOL environment variable to determine which tool is run when none is found Updated scripts for Synopsys VCS and Cadence Xcelium Updated log file creation to first use OsvvmBuild.log and then it is copied to “LogFileDirectory”/”BuildName”.log. Updated Generic Handling Both Simulate and RunTest support callin... »
As I was writing the blog about the 2022.10 Multiple Verification Component example, my focus was drawn to the issue, “How do I call transactions that iterate across an array of verification components?” Solving this issue became the main goal of the 2022.11 release. The 2022.11 release includes: Updated Multiple Verification Component Test Example Created AddressBus and Stream transac... »
Several times now I have been asked how to use multiple OSVVM VC, like a UART, in a simulation. This should be simple, however, there are a couple of VHDL and OSVVM got-yas. For the 2022.10 release, I prepared a basic example that instances 16 UartTx and UartRx components. The good thing about writing test cases like this is that it reveals further opportunities for improvements. As I wrote this a... »