Upcoming Webinars. August 15 Why Should Our Team be Using VHDL + OSVVM for Verification? EU and Early US Session: 7 am PDT / 10 am EDT / 16 CEST US and Evening EU Session: 11 am PDT / 2 pm EDT / 20 CEST August 21 Using OSVVM’s AXI4 Verification Components Part 1 – Creating the AXI4 Testbench (Test Harness) EU and Early US Session: 7 am PDT / 10 am EDT / 16 CEST US and Evening EU Sessi... »
It seems like yesterday that I got back from Verification Futures Conference (June 18) and FPGA Conference Europe (July 2-4) – but it is actually been three weeks now. A big part of that is because as soon as I got back, I have been focused on the OSVVM 2024.07 release – and I tend to get tunnel vision. Verification Futures Conference – June 18 On June 18th I presented Essential ... »
The 2024.05 release adds: Report Updates SPI VC Additions Minor Updates Late Updates – after 2024.05 Report Updates OSVVM automatically generates HTML-based test suite reports, test case reports, and logs that facilitate debugging and provide detailed test artifact collection. OSVVM’s functional coverage reports rival those produced by SystemVerilog vendor tools. OSVVM’s R... »
We have a number of OSVVM class sessions coming up, including in person opportunities in Freiburg, Germany and Bracknell, UK – both of which I am teaching. In addition, we have numerous on-line, instructor led classes. These classes accelerate your learning pace of OSVVM. June 3 to 14 Online Class: 2 weeks, 10 class sessionsInstructor-led, live (interactive) session. Enroll with Sy... »
OSVVM 2024.03 updates can be summarized as: Settings/Configuration Updates Xilinx Update OSVVM Issues Resolved Added Verification Components Minor Updates OSVVM 2024.03a addresses an issue introduced in 2024.03 which calls EndSimulation when a simulation finishes with a TCL error code. This allows VHDL files to be closed that were not properly closed when the simulator exited. Unfortunately... »
Quite some time ago I tried out AMD/Xilinx XSIM in OSVVM. Unfortunately at the time, it was like the Talking Heads song – “We’re on a road to no where” Things have changed. We have heard good things about Vivado Synthesis starting to support VHDL-2019 features – like interfaces. Hear that Siemen’s? Are you going to let AMD Vivado pass you as well as Aldec? So my... »
2023 brought lots of changes. I started traveling again (a little bit). This was my first travels since the start of COVID. I presented papers on OSVVM at SEFUW (ESA’s Space FPGA Users Workshop), MAPLD (NASA’s Military and Aerospace Programmable Logic Devices), FPGA Conference Europe (in Munich), and at Verification Futures (both in Reading UK and Austin TX). OSVVM had 5 updates during... »
The 2023.09a release adds: Scripts: build/include now support Early detection of file or path not found and better error messages. $::ARGV (a TCL array) and $::ARGC $::argv (a TCL list), $::argc and $::argv0 OsvvmSettingsPkg: Package with deferred constants to configure OSVVM settings. RandomPkg – Provides the default value for InitSeed UseNewSeedMethods. AlertLogPkg – Provides the def... »
Abstract Small projects may use a single library for all aspects of the project. As projects increase in size separating different chips into separate VHDL libraries can help avoid naming conflicts. Libraries can also be used to separate different aspects of a project, such as separating the design from the testbench. As a language VHDL makes the usage of libraries easy. Unfortunately, many si... »
Upcoming OSVVM conference/webinar and training classes: September 14 OSVVM in a NutShell, VHDL’s #1 Verification Methodology at Verification Futures Conference Austin, TX in-person and On-line September 18 – 29 On-line Class Session: Advanced VHDL Testbenches and Verification – OSVVM Bootcamp October 16 – 20 In-person Class Session in Bracknell, UK: Advanced VHDL Testbenches and ... »