Author: Jim Lewis
VHDL Functional Coverage is more capable than SystemVerilog
When writing functional coverage it is important to be able to capture all the details of a model. With item (aka point) coverage, both VHDL and SystemVerilog do a good job. However with cross coverage, if the model requires more than a simple Cartesian product, SystemVerilog falls short. OSVVM, on the other hand, offers a rich cross coverage capability. Post continues at SynthWorks OSVVM Blog »
Share your OSVVM story.
Recently Matthias Alles of Creonic shared his OSVVM usage story. I would like to invite you to share how you are using OSVVM. Send a copy of your proposed article to myself (jim at SynthWorks) or Jerry (Jerry at Aldec). From there we can get you setup to post it to the blog. »
Announcing OSVVM Release 2013.04
OSVVM release 2013.04 is now available at OSVVM Downloads. »
IP Encryption (P1735) and VHDL
Currently the IEEE P1076 Working group is reviewing a draft of the proposed IP Encryption (P1735) and accessing how it maps into the pragmas created in VHDL-2008. If you are developing and/or selling VHDL IP that you want to encrypt, you should be participating in this. More details at: https://www.eda.org/twiki/bin/view.cgi/P1076/ To participate, contact Jim at SynthWorks.com »
Why no constraint solver? Are you going to add one?
Nope. No constraint solver. Instead OS-VVM implements an innovative “Intelligent Testbench” feature that does a random walk across functional coverage holes. We call this feature “Intelligent Coverage”. Constraint solvers are yesterday’s verification technology. Intelligent testbenches are the way forward. In his 2011 DVCON address, Mentor Graphics CEO Wally Rhines noted that constrained rand... »