Webinar OSVVM for VHDL Testbenches. Thursday June 25, 2015 Open Source VHDL Verification Methodology (OSVVM) is a comprehensive, advanced VHDL verification methodology. Like UVM, OSVVM is a library of free, open-source code (packages). OSVVM uses this library to implement functional coverage, constrained random tests, and Intelligent Coverage random tests with a conciseness, simplicity and capabil... »
Webinar Thursday June 26, 2014 OSVVM provides functional coverage and randomization utilities that layer on top of your transaction level modeling (tlm) based VHDL testbench. Using these you can create either basic Constrained Random tests or more advanced Intelligent Coverage based Random tests. This simplified approach allows you to utilize advanced randomization techniques when you need them an... »
In conjunction with FirstEDA, I taught the first two European sessions of our OSVVM and Transaction Level Modeling (TLM) focused Advanced VHDL Testbenches and Verification class. We had attendees from many of the major European System Companies who design and verify programmable devices (FPGAs). The skill level of the delegates was impressive and made teaching one of my favorite classes just that ... »
Semi-formal meeting of OS-VVM fans and VHDL users will be held at the 49th Digital Automation Conference (DAC 2012). The conference is located in San Francisco, California, USA this year. The entry to the exhibit hall at Moscone Center is free on Monday, June 4th – drop in if you happen to be in the area. We are meeting at the ALDEC booth (#2126) at 2pm. To help us estimate how many visitors... »