Blog – Page 5 – Open Source VHDL Verification Methodology

VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment

Jim Lewis April 20, 2021 Announcement, VHDL in general 0

IEEE 1076-2019, fondly referred to as VHDL-2019, was approved by IEEE RevCom in September 2019 and published in December 2019. The effort was supported mainly by VHDL users – from requirements definition to LRM writing. This is different from the past where employees of EDA vendors did much of the work – particularly the LRM writing. Language changes were use model driven and had multiple opportun... »

Announcing OSVVM Release 2021.02

Jim Lewis March 4, 2021 OS-VVM in general 0

Up your verification game with the latest from Open Source VHDL Verification Methodology (OSVVM). OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC. About 2021.02 Release 2021.02 i... »

Guest Blog: OSVVM with Verilog Vendor Models by Timothy Stotts

Jim Lewis February 24, 2021 OS-VVM in general 0

Hi, My name is Timothy Stotts, an FPGA and Embedded Systems engineer in upstate New York. There is an often less-discussed technique of adding vendor models to the VHDL test-bench for verifying the peripheral driver and functional behavior of your FPGA design. A quick search on Google shows little documentation on adding IC vendor models to a VHDL test-bench. And during my work experience, the top... »

Space available in March 8-19 OSVVM Bootcamp

Jim Lewis February 23, 2021 Announcement 0

There is still space available in the next OSVVM Bootcamp: Advanced VHDL Testbenches and Verification class. Up level your VHDL verification skills. In Europe, Enroll with FirstEDA at: https://firsteda.com/online-vhdl-training In US + Other Locations, enroll with SynthWorks at: https://synthworks.com/public_vhdl_courses.htm »

OSVVM 2020.12: Virtual Transaction Interfaces

Jim Lewis January 11, 2021 AXI Stream, AXI4, OS-VVM in general 0

OSVVM’s 2020.12 release introduces Virtual Transaction Interfaces (VTIs). VTIs allow us to connect to verification components (VCs) without using any ports or signals in the testbench framework. This capability is important when the verification component is embedded in the design – such as an embedded processor like ZYNQ. In this situation, we want to avoid adding “testben... »

Happy New Year from SynthWorks and OSVVM

Jim Lewis January 1, 2021 AXI Stream, AXI4, Model Independent Transactions, OS-VVM in general, OSVVM Scripting 0

2020 was quite a year. While everything else was quite dark, OSVVM had a great 2020. Normally I travel for work around 75K air miles. 2020 none. This saved a lot of time. All of that time (and more) went into enhancing OSVVM. OSVVM had 6 updates in 2020. This includes the 2020.12 revision which was released late on December 31. More on 2020.12 in a future post. Here are some milestones t... »

VHDL: Shared Variables, Protected Types, and Memory Modeling

Jim Lewis December 16, 2020 Memory Modeling, OS-VVM in general, VHDL in general 0

VHDL-93 (IEEE 1076-1993) created shared variables of an ordinary type as a temporary solution – which was noted in the standard document (aka LRM). VHDL-2000 (IEEE 1076-2000) created protected types as the only type to be used with shared variables and deprecated and removed the usage of a shared variable with an ordinary type. One of the places shared variables of an ordinary type are still use... »

Accelerating Verification Component development with OSVVM Model Independent Transactions

Jim Lewis December 7, 2020 Model Independent Transactions, OS-VVM in general, Verification Components 0

Verification components have become an essential part of a structured VHDL environment. In OSVVM we implement verification components as an entity and architecture. This provides RTL engineers with a familiar environment to create model behavior. The objective of any verification framework is to make the Device Under Test (DUT) “feel like” it has been plugged into the board. Henc... »

OSVVM 2020.10: AXI Stream: Bursting + Full Signaling Support

Jim Lewis November 28, 2020 AXI Stream, Model Independent Transactions, Verification Components 1

The OSVVM 2020.10 release is finally out. Why 2020.10? Yes I realize it is now late November. So why 2020.10? In late October, the code was done and marked as 2020.10 with the expectation that the documentation would be done before the end of the month. The documentation took much longer than I expected and a few other items intervened. Rather than take more time and re-mark the code as 2020.11, i... »

OSVVM Model Independent Transactions

Jim Lewis September 11, 2020 Model Independent Transactions, OS-VVM in general, Verification Components 0

OSVVM Model Independent Transactions I take great joy in reuse – this is true whether it is a plastic bag or VHDL code. OSVVM Model Independent Transactions were added in the 2020.07 release and are directed at improving reuse – and hence bring me great joy. Model Independent Transactions provide two aspects of reuse. First, they simplify verification component development by reducing the number... »