Summary of Changes in 2022.06 Scripting: At build completion, print single-line, text-based build summary Scripting: Improved Error Handling. (continuing from 2022.05) Scripting: Updated HTML log file generation. Log file always created. HTML optionally created Scripting: Optional generation of a do file – for submitting bug reports to vendors Scripting: Added Generic handling for simulate: ... »
Abstract OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have talked about these previously in this webinar series. This webinar focuses on advances in OSVVM data structures. OS... »
Abstract According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging. As a result, we need good scripting to simplify running tests and good reports to simplify debug and help find problems quickly. Scripting can be complicated no matter what language – particularly with EDA tools that need to stay rooted in one directory while it is advantageous ... »
I just posted 2022.05a release. 2022.05 added html transcripts capability to a larger set of tools. Unfortunately this capability requires a new version of TCL that is not supported by older tools, such as Riviera-PRO 2018.02. 2022.05a release fixes this. If you have issues, you can report them in the OSVVM forum, on github issues, or you can send them directly to me. The first two being most reli... »
Abstract Some methodologies (or frameworks) are so complex that you need a script to create initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog + UVM is certainly like this. There are even several organizations that propose that you use their “Lite” or “Easy” approach. Creating a verification component (VC) using OS... »
For some time now, OSVVM has been doing releases every month. Sometimes I talk about them, sometimes they just get posted to the downloads page. Over the past several releases OSVVM has: Improved documentation. Improved our already best in industry test reporting capability. Improved scripting capabilities. Find code coverage tedious – we run, save, merge, and report it in a very simple... »
SynthWorks is continuing with our monthly instructor lead, on-line VHDL classes. With our “half day” on-line format, we do on-line classes right. Accelerate your learning pace of OSVVM. For additional class dates see: https://synthworks.com/public_vhdl_courses.htm We frequently arrange the lecture portion of the OSVVM classes in the early day for US so that our colleagues in Europ... »
Improve your verification capabilities with Open Source VHDL Verification Methodology (OSVVM). OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC. About 2022.02 Release 2022.02 cont... »
OSVVM release 2021.10 focused on improving OSVVM’s reporting capability. In my last post, “OSVVM 2021.10: Build Summary Reports“, I talked about our HTML and JUnit CI reports that allow us to assess whether a set of tests have passed or quickly access which test cases failed. This post features OSVVM’s 2021.10 HTML based Functional Coverage reports. This has been in my mind... »
When we run a set of tests, we need to be able to assess whether all test cases passed or quickly identify which test cases failed. This is the purpose of the OSVVM 2021.10 Build Summary Reports. When tests fail, we need to have detailed information for each test case in a separate report that helps reveal the source of the issue. This is the purpose of the OSVVM 2021.10 Detailed Test Case Reports... »