Several times now I have been asked how to use multiple OSVVM VC, like a UART, in a simulation. This should be simple, however, there are a couple of VHDL and OSVVM got-yas. For the 2022.10 release, I prepared a basic example that instances 16 UartTx and UartRx components. The good thing about writing test cases like this is that it reveals further opportunities for improvements. As I wrote this a... »
Summary of recent changes in OSVVM. Added Ethernet Phy and MAC verification components for GMII, RGMII, MII, RMII Added interrupt handler that supports any verification component that uses the Address Bus Model Independent Interface RandomPkg: added SetRandomSalt as a method to add an offset to all InitSeed calculations – Thanks Torsten M Added demo of using multiple OSVVM VC using “fo... »
Don’t miss your chance to express what verification approach you use for FPGAs (OSVVM) This is the first public survey I have seen. Others have been done by random selection and invitation only. Survey is here »
On GitHub Issues, I had the following question, “With OSVVM scripting (.pro), is there a way to specify testbench generics, waveform files, and length of time to run a simulation.” So lets take a look at these. Lets add to that, where do I get help on OSVVM from? Specifying Generics Every simulator has their own format for specifying generics. With OSVVM, we specify generics by calling... »
Summary of recent changes in OSVVM: Scripts updated for better signaling to continuous integration (CI) tools MemoryPkg updated to remove 31 bit limitation and support storage policies. Reports keep getting better Scripts now support simulating with two top level designs Scripts updated to better support GHDL options and waveforms Scripts now support callbacks to simplify user customization Script... »
Summary of Changes in 2022.06 Scripting: At build completion, print single-line, text-based build summary Scripting: Improved Error Handling. (continuing from 2022.05) Scripting: Updated HTML log file generation. Log file always created. HTML optionally created Scripting: Optional generation of a do file – for submitting bug reports to vendors Scripting: Added Generic handling for simulate: ... »
Abstract OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have talked about these previously in this webinar series. This webinar focuses on advances in OSVVM data structures. OS... »
Abstract According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging. As a result, we need good scripting to simplify running tests and good reports to simplify debug and help find problems quickly. Scripting can be complicated no matter what language – particularly with EDA tools that need to stay rooted in one directory while it is advantageous ... »
I just posted 2022.05a release. 2022.05 added html transcripts capability to a larger set of tools. Unfortunately this capability requires a new version of TCL that is not supported by older tools, such as Riviera-PRO 2018.02. 2022.05a release fixes this. If you have issues, you can report them in the OSVVM forum, on github issues, or you can send them directly to me. The first two being most reli... »
Abstract Some methodologies (or frameworks) are so complex that you need a script to create initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog + UVM is certainly like this. There are even several organizations that propose that you use their “Lite” or “Easy” approach. Creating a verification component (VC) using OS... »