As the developer of Open Source VHDL Verification Methodology (OSVVM) , I would like to invite the Universal VHDL Verification Methodology (UVVM) community to join us in using and developing OSVVM. At this point OSVVM and UVVM are largely duplicating what each other is doing. This wastes valuable time and resources that could be better spent with all of us working toward a common goal. Lets be ... »
In reply to a LinkedIn post that regurgitated the old statement that VHDL is verbose, I replied, “With the VHDL-2008 update, Verilog is more verbose than VHDL.” This led my old friend Cliff Cummings and I to trade a few VHDL vs. System Verilog jabs. One of the things he brought up as concise SystemVerilog verification capabilities are singletons and verification data structures. Rather than give a... »
VHDL + Open Source VHDL Verification Methodology (OSVVM) is great for verification and is a competitor to SystemVerilog + UVM. Especially in the FPGA space where VHDL is the dominant language (see the 2020 Wilson Verification Survey). Some refute this claiming that, “VHDL falls flat on its face when used for verification” and “VHDL can do a lot, however, it cannot do everything S... »
In this second webinar of the VHDL-2019: Just the New Stuff series we will focus on enhancements to VHDL’s protected type capabilities. Protected types simplify and abstract the construction of data structures. As such they are the enabling feature that makes it possible to create VHDL verification methodologies that are competitive with SystemVerilog + UVM, such as Open Source VHDL Verifi... »
IEEE 1076-2019, fondly referred to as VHDL-2019, was approved by IEEE RevCom in September 2019 and published in December 2019. The effort was supported mainly by VHDL users – from requirements definition to LRM writing. This is different from the past where employees of EDA vendors did much of the work – particularly the LRM writing. Language changes were use model driven and had multiple opportun... »
Up your verification game with the latest from Open Source VHDL Verification Methodology (OSVVM). OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC. About 2021.02 Release 2021.02 i... »
Hi, My name is Timothy Stotts, an FPGA and Embedded Systems engineer in upstate New York. There is an often less-discussed technique of adding vendor models to the VHDL test-bench for verifying the peripheral driver and functional behavior of your FPGA design. A quick search on Google shows little documentation on adding IC vendor models to a VHDL test-bench. And during my work experience, the top... »
There is still space available in the next OSVVM Bootcamp: Advanced VHDL Testbenches and Verification class. Up level your VHDL verification skills. In Europe, Enroll with FirstEDA at: https://firsteda.com/online-vhdl-training In US + Other Locations, enroll with SynthWorks at: https://synthworks.com/public_vhdl_courses.htm »
OSVVM’s 2020.12 release introduces Virtual Transaction Interfaces (VTIs). VTIs allow us to connect to verification components (VCs) without using any ports or signals in the testbench framework. This capability is important when the verification component is embedded in the design – such as an embedded processor like ZYNQ. In this situation, we want to avoid adding “testben... »
2020 was quite a year. While everything else was quite dark, OSVVM had a great 2020. Normally I travel for work around 75K air miles. 2020 none. This saved a lot of time. All of that time (and more) went into enhancing OSVVM. OSVVM had 6 updates in 2020. This includes the 2020.12 revision which was released late on December 31. More on 2020.12 in a future post. Here are some milestones t... »