It has been a busy summer for OSVVM. With the world working out of home offices, all of our training has shifted to on-line – which fortunately we started doing 7+ years ago. Not having to travel has freed up additional time that I have devoted to OSVVM development. Updates started with adding PASSED counts to the AlertLog data structure in 2020.05. AXI Full verification components (ma... »
INTRODUCTION Most people don’t think of VHDL as a verification language. However, with the Open Source VHDL Verification Methodology (OSVVM) utility and verification component libraries it is. Using OSVVM we can create readable, powerful, and concise VHDL verification environments (testbenches) whose capabilities are similar to other verification languages, such as SystemVerilog and UVM. Thi... »
Up your VHDL verification game with the latest from Open Source VHDL Verification Methodology (OSVVM). OSVVM 2020.07 focuses on Verification Components. AXI4 Full models were added. Axi4Lite, AxiStream, and UART models were updated to use the new OSVVM Model Independent Transactions. AXI4 (and Axi4Lite) verification components are the most challenging and most interesting I have worked on. O... »
Ever wanted to encapsulate all the signals of an interface (such as AXI4Lite, I2C, …) into a single record only to be confounded by not being able to specify the direction for the elements of the record? In this article we will explore how to do this with either VHDL-2019 interfaces or OSVVM interfaces. VHDL-2019 Interfaces Step 1: A Record is the foundation VHDL-2019 interfaces start with a recor... »
In my earlier post I discussed how you could get around the pre-VHDL-2008 scoping rules by using external names, in this post we will look at using an external name to help us write an OSVVM functional coverage model for the Blackjack state machine shown in figure 1: The aim of our functional model is to create a coverage bin for each state transition so we can ensure that during our tests, every ... »
VHDL-2019 was approved by IEEE RevCom in September 2019 and published in December 2019. It was an effort supported mainly by VHDL users – from requirements definition to LRM writing. This is different from the past where employees of EDA vendors did much of the work – particularly the LRM writing. Language changes were use model driven and had multiple opportunities to be pruned from implementatio... »
Up your verification game with the latest from Open Source VHDL Verification Methodology (OSVVM). OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC. According to the 2018 Wilson Ve... »
There are many things that differentiate VHDL from Verilog. One example, is the ability to use global signals in Verilog, which enables a signal at the top-level to connect to one or more points in the hierarchy. This particular feature is used very effectively by Xilinx, to distribute the Global Set/Reset signal GSR to their IP and cell simulation models. The signal is generated in the glbl.v, wh... »
We are very pleased to post a real example OSVVM experience which has been shared by Miroslav Marinkovic. Miroslav has made use of Functional coverage, Random test generation and Intelligent Coverage Randomization and Message logging and reporting : Alerts and Affirmations in his testbench. We want to test BCH code which provides DEC-TED capability (Double-Error-Correction, Triple-Error-Detection)... »