Activity – Ajeetha Kumari – Open Source VHDL Verification Methodology

Ajeetha Kumari started the topic Using TCover to model bit transitions in the forum OSVVM 1 month, 3 weeks ago

I am adding support for bit vector functional/toggle coverage using OSVVM. I have basic every-bit cover working (Will be glad to share a prototype if anyone is willing to review). Now, the next step is to ensure each bit really transitioned from 0 to 1 and 1 to 0. I tried using TCover and by reading the implementation it looks like it would…[Read more]

Ajeetha Kumari started the topic SBRD: Check API uses AffirmIf, why GetAffirmCount is 0? in the forum OSVVM 11 months ago

SBRD User guide says:
<quote>
Check a received value (ActualType) with value in scoreboard. The Match function is
used to determine if the received and expected values match. Checking is handled by
AffirmIf. As a result, if they match a log PASSED is generated, otherwise, an alert
ERROR is generated.
</quote>

I didn’t create any AlertID (yet),…[Read more]

Ajeetha Kumari replied to the topic SBRD package issue with Modelsim FPGA edition in the forum OSVVM 11 months ago

That worked, thanks. Can we bukcteize this as potential race condition?

Ajeetha Kumari replied to the topic SBRD package issue with Modelsim FPGA edition in the forum OSVVM 11 months ago

I guessed that and did add a 1ns delay before calling NewID – please see the stim process above. Still no luck!

Thanks

Ajeetha Kumari started the topic SBRD package issue with Modelsim FPGA edition in the forum OSVVM 11 months ago

Thanks Jim for the help with MTI version check (18.1 produces a seg-fault with NewID call). Now I have updated to the latest available – 20.1 and I see that seg-fault is resolved. However, during push I get:

<log>
# Time: 1 ns Iteration: 0 Instance: /tb_af_up_dn_counter/u_testcase
# %% Alert FAILURE in OSVVM, Scoreboard Push Index:…[Read more]

Ajeetha Kumari replied to the topic Generic testControlProc – can this be a pattern? in the forum OSVVM 11 months ago

Thanks, aligns with my thoughts. Yes the generator already creates/uses clock/reset procedures.

Regards
Ajeetha

Ajeetha Kumari started the topic Generic testControlProc – can this be a pattern? in the forum OSVVM 11 months ago

Hi there,
Coming from SV/UVM and the concept of design patterns applied to testbenches, am looking for common patterns in a typical OSVVM TB. Things such as:

1. ClockGen
2. ResetGen
3. EndOfTestReport

I believe the above 3 are straightforward (need to add #3 to my generator yet). What about some of the initialization code that I see in TbUart…[Read more]

Ajeetha Kumari replied to the topic GHDL workarounds – any known ones? in the forum OSVVM 11 months ago

Thanks Jim, I understand this better now – it’s scoping issue when multiple types are getting visible to a test.

Regards
Ajeetha

Ajeetha Kumari started the topic GHDL workarounds – any known ones? in the forum OSVVM 11 months ago

I am new here in this forum, am creating a Python based utility to enhance productivity with OSVVM based TBs. One of them is a testbench skeleton generator that should go live shortly (opensource). While navigating some examples I see:

[code]
library OSVVM ;
context OSVVM.OsvvmContext ;
— use osvvm.ScoreboardPkg_slv.all ;
–!! GHDL
use…[Read more]

Ajeetha Kumari

@ajeetha