Ian Gibbins

[Ian Gibbins]

Regarding the example : the code can be updated easily, the documentation requires careful update with it. It is on schedule right now.

I have also received good news – precompiled OS-VVM will be included in the nearest releases of Aldec tools.

[Ian Gibbins]

Hi,

This is known issue in the compiler that is being addressed now. It happens when overloaded function with result type of both vector and its element is used in assignment where the target is an aggregate.
The proper workaround does not require package code change – use qualified expression with function call:
integer_vector'(var. RandCovPoint)
I will update example design to show this option and post when tool fix is available.

Thank you,
Your friendly admin.

[Ian Gibbins]

[Ian Gibbins]

Kuri,

The quick answer is: you cannot do it in a quick and easy manner. You have to do some manual coding to get the required results. Let me explain quickly why:

• implementation of randc is memory hungry: for k-bit number you want to randomize you need at least n=2^k element array to store permutations,
• algorithm for selecting sequences is time consuming and uses resources in very uneven manner.

Here is an outline of the algorithm:

1. Create n-element array A (let’s say that it is indexed 0 to n-1)
2. Fill array A with desired numbers ordered from minimal to maximal
3. Create for loop with counter i and value range n-1 downto 1
4. Within the loop you have to generate random number j from the range 0 to i and
   
5. Swap A(i) with A(j) and go to the next loop iteration
6. Initialize randc counter r to 0
7. For each randc call return A(r) and increment r
8. When r reaches n, jump to step 3.

As you see, flexible implementation of this algorithm requires smart decisions to balance memory usage and execution speed. We will investigate further, but for now I recommend creating fixed implementation suited to your particular needs.

One more thing, SV implementation of randc that meets  LRM requirements cannot be really random! I will post explanation in the blog section soon.

Your Admin

[Ian Gibbins]

One more thing: your code samples coverage data on the same clock edge that triggers counting. It means that currect active clock edge samples data triggered by previous active clock edge. The side effect is that your code will never display results containing anything in bin 7, because database dump condition is reached before “111” data can be sampled. You can use either delayed clock for sampling or sample on the other clock edge. The code that should let you get full coverage is presented below:

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std_unsigned.all;
use work.CoveragePkg.all;

entity counter is
 port (CLK : in std_logic ;
       RST : in std_logic ;
       OUTA : out std_ulogic_vector (2 downto 0)
 ) ;
end counter ;

architecture RTL of counter is
  signal cnto :std_logic_vector(2 downto 0);
  shared variable test_cover : CovPType ;

begin

test_cover.AddBins(GenBin(0,7,8));

process (CLK,RST) begin
  if RST='0' then
    cnto <= (others=>'0') ;
  elsif (CLK'event and CLK='1') then
    cnto <= cnto + '1';
  end if ;
end process ;

process (CLK) begin
  if (CLK'event and CLK='0') then
    test_cover.ICover(to_integer (cnto));
  end if;
end process ;

process (CLK) begin
  if (CLK'event and CLK='1') then
    if (cnto="111") then
      test_cover.WriteCovDb ("test_cover.txt", OpenKind => WRITE_MODE );
      test_cover.WriteBin;
    end if ;
  end if;
end process ;

OUTA <= cnto;

end RTL ;

[Ian Gibbins]

Kuri,

Two issues with your code:

1. You are using ‘std_logic_unsigned‘ package which can cause serious problems when mixed with VHDL-2008 code. Long story short: if your system contains ‘std_logic_unsigned‘ precompiled in VHDL-2002 mode and you try to use it together with OS-VVM packages compiled in VHDL-2008 mode, logic types internal markers in the libraries will be incompatible in both. You may get no errors/warnings during your design compilation, or receive confusing messages stating that subprograms cannot be found for given argument types. Please use NUMERIC_STD_UNSIGNED that was added to VHDL-2008 specifically for the same purposes as ‘std_logic_unsigned‘, but avoids numerous problems in the older package.
2. Once you replace package in the design unit header, there is one more issue left: you are creating 8 INTEGER bins, so the data sampled in the data collection process should be INTEGER, not INTEGER_VECTOR. Please replace test_cover.ICover(to_integer_vector (cnto)); with test_cover.ICover(to_integer (cnto));.

After those two changes you should get correct results.

BTW, the replies in Forums are treated as HTML code (with different tags allowed for different levels of users). List of allowed tags is always presented below the entry field. It means that not allowed tags will be stripped before posting, and ‘less than’ and ‘greater than’ characters may be treated as parts of tag. You can either escape those characters, or in case of VHDL code export it to HTML from some popular editor (Notepad++, Programmer’s Notepad, etc.) and then paste exported HTML to the reply.

[Ian Gibbins]

[Author]

Posts