Activity – Isaac – Open Source VHDL Verification Methodology

@isaacv

Active 3 weeks, 6 days ago

Isaac replied to the topic Using VCs without the built-in Scripts – but instead VUnit in the forum OSVVM 3 weeks, 6 days ago

Hi Jim,

thanks a lot for the quick reply and, of course, for all the work you put into the OSVVM.

If I understand you correctly, I could either a) build the OSVVM libraries with the built-in scripts, and then link to those libraries in my workflow, or b) take a look at the scripts, specially VendorScripts_Siemens.tcl, and reverse-engineer the…[Read more]
Isaac started the topic Using VCs without the built-in Scripts – but instead VUnit in the forum OSVVM 3 weeks, 6 days ago

Hi everyone,

currently I’m setting up a verification environment with an AXI (Full) verification component (VC) at work. I’ve ran several demos in the past using the built-in Scripts, however, now I would like to compile everything from scratch to target our verification environment (Questa + VUnit). My question is: is there a recommended way to…[Read more]
Isaac became a registered member 1 year, 4 months ago