Why no constraint solver? Are you going to add one?
Nope. No constraint solver. Instead OS-VVM implements an innovative “Intelligent Testbench” feature that does a random walk across functional coverage holes. We call this feature “Intelligent Coverage”.
Constraint solvers are yesterday’s verification technology. Intelligent testbenches are the way forward. In his 2011 DVCON address, Mentor Graphics CEO Wally Rhines noted that constrained random environments generate a significant number of redundant vectors on their way to functional coverage closure. Randomization theory tells us that a good constraint solver will take O(N * log N) randomizations to generate N different test cases. The log N factor correlates with Mentor’s observation of a 10X to 100X speedup when using an intelligent testbench tool.
With OS-VVM, intelligent coverage is built into CoveragePkg. As a result, it is code feature rather than a tool feature – and it is free.
The focus of the next set of enhancements planned for the OS-VVM packages is to further enhance the “Intelligent Coverage” features. These steps will move OS-VVM further ahead of other verification languages.
Furthermore, since OS-VVM randomizes across functional coverage holes, it provides a naturally balanced solution. As a supplement to intelligent coverage, the sequential constrained random methodology provided by RandomPkg is sufficient for the time being.
For more information on OS-VVM’s coverage modeling and randomization methods, see CoveragePkg_user_guide.pdf and RandomPkg_user_guide.pdf (both in the download zip file). This material plus additional advanced techniques are covered in the class, VHDL Testbenches and Verification – OSVVM Bootcamp.