Activity – Open Source VHDL Verification Methodology

Hassan started the topic Does VHDL contain functions like Verilog $readmemb and $readmemh? in the forum VHDL 9 months, 3 weeks ago

Verilog/SystemVerilog (synthesis) has some functions that can read a file into a signal. These are $readmemb and $readmemh. These can both be used to easily create a ROM from file contents. As far as I know, VHDL does not contain anything along these lines that will work in synthesis. Is this true? If so, why is this so?
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Hassan started the topic Why does VHDL require explicit conversion from signed/unsigned to logic vector? in the forum VHDL 9 months, 3 weeks ago

The signed, unsigned and std_logic_vector are all ultimately based on the std_logic. Why does VHDL require explicit conversion from signed to std_logic_vector and unsigned to std_logic_vector?
Hassan replied to the topic The #if in VHDL in the forum VHDL 9 months, 3 weeks ago

If the design has variants that are controlled using #if e.g lets say we have FEATURE1, FEATURE2, FEATURE3VER and in SystemVerilog it could be written like this:

#if FEATURE1

#endif

#if FEATURE2

#if FEATURE3VER > 2

#else

#endif

#endif

How can this be written using VHDL-2019 Conditional Analysis and how will the things used in the #if be…[Read more]
Hassan replied to the topic Convert std_logic_vector to record in the forum VHDL 9 months, 3 weeks ago

One more thing I would say about evolving the language is that, it should have more regular updates. We had more than 10 years between VHDL 2008 and then VHDL 2019. There should be some minor updated every few years maybe 2 or 3 years. A new standard comes after more than 10 years and then the vendors take another 10 years to support more than…[Read more]
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Jim Lewis replied to the topic Convert std_logic_vector to record in the forum VHDL 9 months, 3 weeks ago

Hassan,
The way languages get enhanced is for people like yourself to go to the working group web page and make proposals and contribute to the development effort.

For VHDL, the appropriate place to make proposals is at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/

VHDL in particular is a volunteer driven standard. Hence, it is…[Read more]
Hassan started the topic Convert std_logic_vector to record in the forum VHDL 9 months, 3 weeks ago

Lets take an example,

constant field2_len : integer := 8;
constant field3_len : integer := 4;
constant myrecord_len : integer := 1 + field2_len + field3_len;

type MyRecord is record
field1 : std_logic;
field2 : std_logic_vector(field2_len-1 downto 0);
field3 : std_logic_vector(field3_len-1 downto 0);
end record MyRecord;

Now…[Read more]
Jim Lewis replied to the topic Creating Asynchronous Clocks in the forum OSVVM 9 months, 3 weeks ago

2024.07 updates CreateClock. They are breaking changes – meaning the way clock starts up is different. There was alot of unneeded complexity that was part of the old CreateClock that has been minimized – while still keeping clock changing at simulation cycle 0 (aka delta cycle 0).

If you want to preview it, see the Dev branch. Nominally it…[Read more]
Jim Lewis replied to the topic case splitting in the forum OSVVM 9 months, 3 weeks ago

Just a quick note, release 2024.07 will have a CreateJitterClock:

`
procedure CreateJitterClock (
signal Clk : inout std_logic ;
signal CoverID : inout CoverageIdType ;
constant Name : in string ;
constant Period : in time ;
constant DutyCycle : in real := 0.5 ;…[Read more]
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Jim Lewis replied to the topic Mixed language simulation and synthesis support in the forum VHDL 10 months ago

The IEEE group that works on EDA standards in general and spawns out groups like the IEEE 1076 WG is named DASC. You can find their website here: https://dasc.org/ You can certainly work through them to form such a working group.
Jim Lewis replied to the topic VHDL Assert that prints the entity instance name and path in the forum VHDL 10 months ago

You should be able to surround the process with
`– synthesis translate_off
process …
end process;
— synthesis translate_on
Hassan started the topic Mixed language simulation and synthesis support in the forum VHDL 10 months ago

One way in which hardware engineers are suffering is that there exist more than one RTL language and both of these can be used for writing testbenches although SystemVerilog has gone ahead since it was created from Verilog by integrating Hardware Verification Language features.

A serious issue that exists is that there is no set standard (from…[Read more]
Hassan replied to the topic The #if in VHDL in the forum VHDL 10 months ago

Doesn’t that feature only work with these things:

`if (TOOL_VENDOR = “Aldec”) and (TOOL_NAME = “Riviera-PRO”) then
constant VHDL_2019_STATUS : string := “With Aldec VHDL-2019 is here” ;

How will it work with things besides TOOL_VENDOR and TOOL_NAME? I do not understand why this feature has not been in VHDL from the start.

I mean using #if we…[Read more]
Jim Lewis replied to the topic Interrupt Handling in OSVVM AddressBus Model Independent Transactions in the forum OSVVM 10 months ago

Hi Lars,
OSVVM has an InterruptHandler.vhd in OsvvmLibraries/Common/Src. It handles switching records for you. When there is no interrupt pending, it connects the transaction record of TransRec to the AddressBus VC (such as Axi4Manager or Axi4LiteManager). When an interrupt is pending it connects the InterruptRec to the AddressBusVC.

The…[Read more]
Jim Lewis replied to the topic The #if in VHDL in the forum VHDL 10 months ago

Hi Hassan,
It is part of VHDL-2019. It is called Conditional Analysis. I have heard that vendors support it in older revisions.

For details, see my presentation, VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and Environment. I did this through Aldec as one of their events. You should be able to register…[Read more]
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