Activity

For the next release of OSVVM, I have added an AlertLogID input to SafeResize and all of the OSVVM VC specify the ID on the call to SafeResize. I also updated the error message to be of the following form:

Alert ERROR in AxiManager_1, SafeResize: value changed on resize. Original value: 01AF, Resized value: AF

Hopefully this will…[Read more]

Step 1: If you have complex clock domain crossings, you probably need a clock domain crossing tool. Especially to find anything that might loop back.
Step 2: Use your directed cases to explore the relationships you understand.
Step 3: Add jitter to your clock (or clocks depending on the number of clock domains you have) so that your…[Read more]

Me too. What is about Jitter Simulation with min/max definitions of the phase to simulate short term jitter effects?

Although old, a late response: This topic is often discussed together with pull ups constrained in the XDC for a pin which hardly can be simulated. Together with timing demands and driver issues, which are the common problems at I2C I recommend to use an analog behaviour model which transforms both the outout of the VHDL Pin and its input to a…[Read more]

I think the complaint refers to the issue that the testbenches and example code for the design more and more is limited to Verilog for an unknown reason. Recently I again stumbled over a thing: A DDR Design cannot be built with an AXI-Interface in VHDL. The AXI is only available for Verilog.

Xilinx disreagards the fact that VHDL has certain…[Read more]