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Step 1: If you have complex clock domain crossings, you probably need a clock domain crossing tool. Especially to find anything that might loop back.
Step 2: Use your directed cases to explore the relationships you understand.
Step 3: Add jitter to your clock (or clocks depending on the number of clock domains you have) so that your…[Read more]

Me too. What is about Jitter Simulation with min/max definitions of the phase to simulate short term jitter effects?

Although old, a late response: This topic is often discussed together with pull ups constrained in the XDC for a pin which hardly can be simulated. Together with timing demands and driver issues, which are the common problems at I2C I recommend to use an analog behaviour model which transforms both the outout of the VHDL Pin and its input to a…[Read more]

I think the complaint refers to the issue that the testbenches and example code for the design more and more is limited to Verilog for an unknown reason. Recently I again stumbled over a thing: A DDR Design cannot be built with an AXI-Interface in VHDL. The AXI is only available for Verilog.

Xilinx disreagards the fact that VHDL has certain…[Read more]

Questa Intel, yes.

Thanks for the info Jim! I was dealing with some unusual sizes for logic vectors. So, I just resized them in my VC to have a bigger width to capture all of the data since I actually wanted to capture all of the data bits, not just some of them. I now don’t get this error anymore.

Hi Joseph,
This is coming from the call to SafeResize that is inside of OSVVM verification components. What it is telling you is that the testbench put a value with more one’s on the left hand side of it in the call to a transaction, such as Write, Read, or Send, than is used by the verification component.

The error will happen when you call…[Read more]