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Agreed that SetDebugMode is enough for what you are doing. SetInteractiveMode = SetDebugMode + SetLogSignals + Stop Simulation when analyze or simulate error occurs.

I use SetInteractiveMode false when running a set of simulations in CI or as a regression as I want to see results from all tests, but SetInteractiveMode when debugging.

Thank you for this detailed response – very informative.

I found the TestDone signal in my simulator (was looking for it in the wrong part of the hierarchy) and it behaves as expected. FYI I am only using SetDebugMode and did not need to use SetInteractiveMode.

Hi Adam,
Adding random delays is a work in progress. I am posted about updates in https://osvvm.org/forums/topic/learning-osvvm-with-axi4#post-2209.

Best Regards,
Jim

Hi Adam,
I just pushed a new version of Axi4Manager.vhd with random delays. They maintain backward compatibility, and hence, you have to turn on the randomization features. No documentation yet. I still have to add random delays to Axi4Memory and Axi4Subordinate – I also need to add them to the VTI versions of the VC. Also the initial delay…[Read more]

Hi Jason,
Resolution functions are a VHDL-1987 feature. So Ashenden’s VHDL Designers Guide should have a good description of them. I will describe them briefly here too.

In VHDL-2008, element based resolution functions were extended to support array objects. So std_logic_vector is now defined as:
subtype std_logic_vector is (resolved)…[Read more]

Hi Adam,
WRT randomness in dispatching each channel, that is what I am currently working on. I added it to AxiStream in a Beta form in an earlier OSVVM release – it has changed some on the Dev branch. I will be adding it to Axi4 VC next. Each channel will be independent, so a write data should randomly happen prior to write address, as will…[Read more]

Vivado 2022.2 simulator states to supports VHDL-2008. While this is meant to mean full support, there certainly are still many issues present. The focus was probably to support language features already supported in synthesis.

I personally tested support for VHDL-2008 fixed point number libraries, which require generic packages.

Vivado 2023.1…[Read more]