Activity

Hi Adam,
I have added some beta features to the 2023.04 release to see if we can address this better. As a Beta feature, there is no documentation yet – as it may change. See AxiStream/TestCases/TbStream_SendGetRandom1.vhd.

Best Regards,
Jim

Hi Adam,
Not yet. Are you interested in doing a pull request against TbUtilPkg?

Best Regards,
Jim

I just want to post my test_harness.pro and testbench.pro files here so you may understand me more clearly. But every time I post the code, it is rejected. How can I post a code segment here?

Hi Jim,

thanks for the explanation. If I make the .tcl script the TestCaseName, it will be sourced and the RAM is successfully initialized during the simulation. But I think it is sourced as <TestCaseName>.tcl but not <LibraryUnit>.tcl. Because with any other name it will not be sourced, at least in my project. I have tried testbench name,…[Read more]

Hi Jim,

thanks for the explanation. I tried to post some more detail but I got this:
A potentially unsafe operation has been detected in your request to this site
Your access to this service has been limited. (HTTP response code 403)

If you think you have been blocked in error, contact the owner of this site for assistance.

Block Technical…[Read more]

LibraryUnit in this case is the name which you used with simulate, hence, either the name of your testbench or configuration that runs your testbench. Often, I try to make this the same as the TextCaseName, but it does not have to be.

In VHDL, LibraryUnit is an analyzed Design Unit and from the LRM,

A design unit is
either an entity…

[Read more]