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Thomas became a registered member 2 years, 7 months ago
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Oliver replied to the topic Verification with SystemVerilog or VHDL in the forum OSVVM 2 years, 7 months ago
Hi Jim,
thanks for the link. Now that I finally got my tools working I will have a look at it soon. The OSVVM demo tests look good and run well (not when following the old user’s guide in the OSVVM Examples zip archive on this site though). Unfortunately the simulation of Xilinx PCIe-demo-design with Vivado will not run when the language is set to…[Read more] -
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Juan became a registered member 2 years, 8 months ago
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Adrian Simionescu's profile was updated 2 years, 8 months ago
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Mickael became a registered member 2 years, 8 months ago
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yoimiya became a registered member 2 years, 8 months ago
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Taha became a registered member 2 years, 8 months ago
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Li became a registered member 2 years, 8 months ago
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Yacine became a registered member 2 years, 8 months ago
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Jim Lewis wrote a new post 2 years, 9 months ago
Summary of 2022.12 ChangesUpdated StartUp.tcl to use OSVVM_TOOL environment variable to determine which tool is run when none is found
Updated scripts for Synopsys VCS and Cadence Xcelium […]
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Christophe became a registered member 2 years, 9 months ago
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Tim became a registered member 2 years, 9 months ago
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Jim Lewis replied to the topic Questa-Intel & Reports in the forum OSVVM 2 years, 9 months ago
Is that the Questa Intel edition or another edition?
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Andrei became a registered member 2 years, 9 months ago
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Jim Lewis replied to the topic Expected alerts generation in the forum OSVVM 2 years, 9 months ago
Hi Anna,
Two thoughts on that.First, there is no need for an expected SLVERR to be an actual test case error. The following is from p37 of the Axi4_VC_user_guide.pdf that is in the documentation repository:
By default, the expected value for BRESP and RRESP are OKAY. When testing a subordinates response to an incorrect address, a SLVERR is…[Read more]
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Anna started the topic Expected alerts generation in the forum OSVVM 2 years, 9 months ago
Hello All,
Is there a way in OSVVM for the simulation to successfully pass after predefined number of errors is generated? To check for example if the AXI Slave correctly generates SLVERR.
Thanks!
Anna - Load More
