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Hi Jim,

thank you for the detailed answers!

Actually I’m looking at the PCIe test framework from Xilinx. The AXI I’m planning to verify is already included in OSVVM, as I could see. For QSPI as another task I will probably need to write my own.

Best regards
Oliver

Hi Antonio,
I did some testing with Synopsys over the last week.

It looks like when I added the error handling to the scripts, it broke the scripts for Synopsys. Unfortunately at the time I added the error handling to other aspects of the scripts, I did not have active Synopsys licenses.

I have updated the scripts now and they are working…[Read more]

Hi Michael,
Sorry I missed your post.

OSVVM pro scripts are a abstract procedure layer on top of TCL. Hence, you can do anything that TCL does. See the scripts OsvvmLibraries/OsvvmLibraries.pro and OsvvmLibraries/osvvm/osvvm.pro for examples.

Best Regards,
Jim

Hi Steve,
I did some testing with Cadence over the last week. Looks like the 2022.08 updates to memory pkg broke some things. On the dev branch of OSVVM, I moved MemoryPkg_c.vhd back to the 2022.06 version.

It also looks like Cadence is failing the singleton tests in CoveragePkg. I need to try to find root cause as the singleton tests in…[Read more]

Hi Oliver,
> Above all, there is no SystemVHDL as a complement to the SystemVerilog
Renaming Verilog to SystemVerilog is simply marketing. Just asking that question demonstrates the brilliance it.

OSVVM provides VHDL with “SystemVerilog + UVM” verification capabilities including Transaction Level Modeling, Constrained Random, Functional…[Read more]

Hi Thomas,
I try to divide the concerns into what must be done for every transaction and what is stable for a long period of time. Things that are stable for a long period of time can be set with SetModelOptions.

The error injection probability is a candidate for SetModelOptions.

You may wish for things like Image Width, Height, Color Depth,…[Read more]

Hi Jim,
Thank you for your elaborate (and much appreciated) reply.
It is very useful and confirms what I feared being the case: that this is in fact a memory leak…
The first solution you suggest was actually already on my mind as a working alternative (without the memory leak). But this approach has the side-effect that an additional ‘copy…[Read more]

Memory leak. I do not think the simulators are able to handle this for you.

I should note general VHDL questions like this may get a response faster on StackOverflow, however, I have indeed encountered this one and know a couple of solutions.

The simplest that I have seen, but not used (so it may have flaws) is:

`vhdl
function my_function(obj…[Read more]