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Marco became a registered member 5 years, 5 months ago
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Hassan became a registered member 5 years, 5 months ago
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Osman became a registered member 5 years, 5 months ago
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Jim Lewis replied to the topic Intelligent Coverage Random test generation in the forum OSVVM 5 years, 5 months ago
Hi Ken,
Yes and no. SV does not have this built into it or the UVM library.OTOH, Accellera created a language that layers on top of other languages (I think VHDL too), called PSS (Portable Test and Stimulus Standard). Of course, it adds another layer of $$$$$ to your simulator budget.
Best Regards,
Jim -
Cahit's profile was updated 5 years, 5 months ago
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Ken Campbell started the topic Intelligent Coverage Random test generation in the forum OSVVM 5 years, 5 months ago
Hello everyone.
I just wanted to point out, and correct me if I am wrong, OSVVM is the only method that has Intelligent Coverage Random test generation. SV does not. This is a major plus for OSVVM.
If in fact only OSVVM provides this feature, I think it should be more obviously stated as a step above or an advantage over other methods.
Ken
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Ahmad became a registered member 5 years, 5 months ago
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Andrii became a registered member 5 years, 5 months ago
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Tobias's profile was updated 5 years, 5 months ago
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Martin became a registered member 5 years, 5 months ago
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Jim Lewis wrote a new post 5 years, 5 months ago
Over the last year, OSVVM has been growing rapidly. I was delighted to have the opportunity to present OSVVM papers at FPGA World (both Stockholm and Copenhagen) and at DVCon Europe in Munich. In addition, between […]
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Evert Scholtz's profile was updated 5 years, 5 months ago
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Maksim's profile was updated 5 years, 5 months ago
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Qing became a registered member 5 years, 5 months ago
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Ian Gibbins wrote a new post 5 years, 5 months ago
Open Source VHDL Verification Methodology (OSVVM) has been named the number #1 VHDL Verification Library by The 2018 Wilson Research Group ASIC and FPGA Functional Verification Study.
While your EDA vendor may […]
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Ian Gibbins wrote a new post 5 years, 5 months ago
In the latest release of Open Source VHDL Verification Methodology (OSVVM), all licenses for the entire OSVVM library (utility and model libraries) were updated to Apache 2.0 license. This is being done in p […]
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Jim Lewis wrote a new post 5 years, 5 months ago
Open Source VHDL Verification Methodology (OSVVM) simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, […]
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I was wondering, if the webinar is recorded – and if yes, how to access it – for the OSVVM enthusiast, who unfortunately missed the event?
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Hi Cahit,
Yes it will be posted shortly at Aldec (the good folks who hosted the webinar).Best Regards,
Jim-
Looking forward to it 🙂
Thanks Jim.
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Hi Cahit,
Here is the link to the recorded webinar. To get to it, you need to register with Aldec (who hosted the webinar).
https://www.aldec.com/en/support/resources/multimedia/webinars/2083Best Regards,
Jim
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Feda Demo became a registered member 5 years, 6 months ago
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Sebastian Zanker replied to the topic OSVVM and Cadence Simulator in the forum OSVVM 6 years, 11 months ago
Hi Jim,I mailed the log files to your Synthworks Mail.Kind regardsSebastian
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Jim Lewis replied to the topic Coverage and sequences in the forum OSVVM 6 years, 11 months ago
Sure, it is easy. Sequences imply history. We create history explicitly just like RTL – by using clocked processes / flip-flops. Once you have history, this is just a simple cross product of selected current values and two previous values. WRT sampling, in OSVVM, we trigger on transaction completion using an explicit call to…
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