OSVVM Webinar December 15 and Classes
Webinar From OSVVM to UCIS Database. Thursday December 15, 2016
When a simulator records functional coverage internally, it gains the ability to correlate the functional coverage with its verification planning tools and share that information with safety critical tools.
The 2016.11 release of Open Source VHDL Verification Methodology (OSVVM) adds an API to record OSVVM Functional Coverage directly into a simulator’s UCIS database.
This task has been on our todo list for quite some time. UCIS is complicated. Fortunately the engineers at Aldec were up to creating an initial implementation. Together we revised it.
Join OSVVM architect and VHDL trainer, Jim Lewis, and Aldec Software Product Manager, Radek Nawrot, for a presentation and demonstration of how to add this capability to your VHDL testbench.
|Europe Session||3-4 pm CET||6-7 am PST||9-10 am EST||Enroll with Aldec|
|US Session||11 am -12 noon PST||2-3 pm EST||8-9 pm CET||Enroll with Aldec|
OSVVM World Tour Training Dates
VHDL Testbenches and Verification – OSVVM+ Boot Camp
Learn the latest VHDL verification techniques including transaction level modeling (tlm), self-checking, scoreboards, memory modeling, functional coverage, directed, algorithmic, constrained random, and intelligent testbench test generation. Create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog or ‘e’. Our techniques work on VHDL simulators without additional licenses and are accessible to RTL engineers.
|January 16-20 and January 30-February 3||Web Class||Enroll with SynthWorks|
|February 20-25||Freiburg, Germany||Enroll with PLC2|
|March 6-10||Nordic Region||Enroll with FirstEDA|
|March 13-17 and March 27-31||Web Class||Enroll with SynthWorks|
|April 17-21 and May 1-5||Web Class||Enroll with SynthWorks|
|May 8-12||Freiburg, Germany||Enroll with PLC2|
|May 22-26||Bracknell, UK||Enroll with FirstEDA|