Announcing OSVVM Release 2021.02
Up your verification game with the latest from Open Source VHDL Verification Methodology (OSVVM).
OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC.
Release 2021.02 is mainly an incremental maintenance release. It updates and/or adds:
- Updated Scripts to better support Aldec’s Active-HDL and GHDL
- In AXI4 and AxiStream components added Valid Delays
- Added Multiple driver detection
- Added New RequestTransaction/WaitForTransaction to support integer
Getting Started with OSVVM
The fastest way to get started with OSVVM is SynthWorks’ Advanced VHDL Testbenches and Verification which is available world wide either on-line or on-site (once we can travel again). Here is our current class schedule. The next class dates are:
- April 12 – 23
- May 10 – 21
- June 7 – 18