OSVVM: Verification Data Structures & Singletons
In reply to a LinkedIn post that regurgitated the old statement that VHDL is verbose, I replied, “With the VHDL-2008 update, Verilog is more verbose than VHDL.” This led my old friend Cliff Cummings and I to trade a few VHDL vs. System Verilog jabs. One of the things he brought up as concise SystemVerilog verification capabilities are singletons and verification data structures. Rather than give a... »