OSVVM 2024.03 updates can be summarized as: Settings/Configuration Updates Xilinx Update OSVVM Issues Resolved Added Verification Components Minor Updates OSVVM 2024.03a addresses an issue introduced in 2024.03 which calls EndSimulation when a simulation finishes with a TCL error code. This allows VHDL files to be closed that were not properly closed when the simulator exited. Unfortunately... »
Quite some time ago I tried out AMD/Xilinx XSIM in OSVVM. Unfortunately at the time, it was like the Talking Heads song – “We’re on a road to no where” Things have changed. We have heard good things about Vivado Synthesis starting to support VHDL-2019 features – like interfaces. Hear that Siemen’s? Are you going to let AMD Vivado pass you as well as Aldec? So my... »
2023 brought lots of changes. I started traveling again (a little bit). This was my first travels since the start of COVID. I presented papers on OSVVM at SEFUW (ESA’s Space FPGA Users Workshop), MAPLD (NASA’s Military and Aerospace Programmable Logic Devices), FPGA Conference Europe (in Munich), and at Verification Futures (both in Reading UK and Austin TX). OSVVM had 5 updates during... »
The 2023.09a release adds: Scripts: build/include now support Early detection of file or path not found and better error messages. $::ARGV (a TCL array) and $::ARGC $::argv (a TCL list), $::argc and $::argv0 OsvvmSettingsPkg: Package with deferred constants to configure OSVVM settings. RandomPkg – Provides the default value for InitSeed UseNewSeedMethods. AlertLogPkg – Provides the def... »
Abstract Small projects may use a single library for all aspects of the project. As projects increase in size separating different chips into separate VHDL libraries can help avoid naming conflicts. Libraries can also be used to separate different aspects of a project, such as separating the design from the testbench. As a language VHDL makes the usage of libraries easy. Unfortunately, many si... »
Upcoming OSVVM conference/webinar and training classes: September 14 OSVVM in a NutShell, VHDL’s #1 Verification Methodology at Verification Futures Conference Austin, TX in-person and On-line September 18 – 29 On-line Class Session: Advanced VHDL Testbenches and Verification – OSVVM Bootcamp October 16 – 20 In-person Class Session in Bracknell, UK: Advanced VHDL Testbenches and ... »
OSVVM release 2023.07 updates OSVVM’s Requirement Tracking (aka Specification Tracking) capability so that HTML and CSV based merged requirements reports are produced automatically. Requirements Tracking (Part 1) started with the 2020.08 release. In the 2020.08 release, each test could write out a CSV requirements report. The expectation was that external requirements tools imported these and merg... »
Summary of 2023.07 Changes AlertLogPkg: Added WriteRequirementsYaml to write requirements for a test case into a YAML file ReportPkg: In EndOfTestReports if GotRequirements it calls WriteRequirementsYaml. Hence saving requirements is automatic. Scripts: For each test suite, merges the requirements yaml files for each test case and produces a test suite requirements HTML Scripts: For each bu... »
Introduction The OSVVM co-simulation environment has the ability to generate transactions from C++ to drive various virtual components (VCs), such as AxiBus, AxiStream, Ethernet, Uart, dual port RAM etc. But did you know that you can drive multiple VCs from within the same test bench, all driven by C++ software? To do this we have the concept of ‘nodes’. The OSVVM co-simulation documentation does ... »
Summary of 2023.05 Changes Co-simulation updates Added split transaction methods for address bus model independent manager Added support address bus model independent subordinate/responder Added support for streaming bus model independent transactions Added test data pattern generation methods Added data check methods AxiStreamTransmitter and AxiStreamReceiver VC: Randomize delays for TVali... »