Activity – David Clift – Open Source VHDL Verification Methodology

David Clift

David Clift replied to the topic At the end of the simulation, AlertLogPkg.vhd must open. causes error message. in the forum OSVVM 7 months ago

Hi Jeremy,

If you are using Riviera-PRO, you can stop the GUI from opening the terminating VHDL file by unsettling “Open editor when simulation is interrupted from source code.” You will find this in Tools –>Preference under Debug–>General.

I hope this helps.
Regards
David…
David Clift replied to the topic OSVVM in DO-254 DAL A-B in the forum OSVVM 2 years, 8 months ago

Hi Daniel,

Thank you for your post. Whilst I agree that in general UVM is the number one verification framework for ASICS and FPGAs as seen in the 2020 Wilson research surveys. These statistics do not tell the full story as these results are across all industry segments. For DO-254 designs, we still see VHDL as the number one testbench language,…[Read more]
David Clift commented on the post, OSVVM FSM Coverage Modelling 4 years, 5 months ago

Hi Miroslav,
Thank you for your kind comments and encouragement, I am glad my post was helpful, hopefully you will find my upcoming post useful as well.
With regards to your questions:
1. Could you use concatenation to shorten the code? Probably, I haven’t tried it. Typically I tend to write things out longhand so to speak, as you see here each…[Read more]

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David Clift wrote a new post 4 years, 5 months ago

In my earlier post I discussed how you could get around the pre-VHDL-2008 scoping rules by using external names, in this post we will look at using an external name to help us write an OSVVM functional coverage […]
- Miroslav Marinkovic replied 4 years, 5 months ago
  
  Hi David,
  
  Thanks for nice post, it is quite useful.
  
  I have a few comments:
  1. If we want fewer lines of the code, we can combine Bins using concatenation &, for example :
  
  — Test21
  FSM_CP.AddCross(“Test21”, GenBin(BlackJack_type’POS(Test21)),
  GenBin(BlackJack_type’POS(BustState)) & GenBin(BlackJack_type’POS(HoldState)) & GenBin(BlackJack_type’POS(TenBack)));
  
  2. As an alternative to the approach in the post,
  it is good idea to separate the coverage model and the coverage collector in two processes:
  
  COVERAGE_MODEL: process
  begin
  — Begin_g
  FSM_CP.AddCross(“Begin_g to Hit_me”,
  GenBin(BlackJack_type’POS(Begin_g)),
  GenBin(BlackJack_type’POS(H1_Hit_me)));
  .
  .
  .
  — Mark rest as illegal.
  FSM_CP.AddCross(ALL_ILLEGAL, ALL_ILLEGAL);
  wait;
  
  end process COVERAGE_MODEL;
  
  COVERAGE_COLLECTOR: process
  constant COMBINATIONAL_DELAY : time := 1 ns;
  alias current_state is <>;
  alias next_state is <>;
  begin
  
  wait until rising_edge(clk);
  wait for COMBINATIONAL_DELAY;
  — update coverage information
  v_fsm_transition_coverage.ICover( (BlackJack_type’POS(current_state), BlackJack_type’POS(next_state)) );
  
  end process COVERAGE_COLLECTOR;
  
  Regarding the external names used in COVERAGE_COLLECTOR process, it is assumed that RTL code of the FSM contains the process for FSM state register.
  Something as:
  
  STATE_REG: process(clk, reset_n)
  begin
  if reset_n = ‘0’ then
  current_state <= Begin_g;
  elsif rising_edge(clk) then
  current_state <= next_state;
  end if;
  end process STATE_REG;
  
  Best regards,
  Miroslav
- David Clift replied 4 years, 5 months ago
  
  Hi Miroslav,
  Thank you for your kind comments and encouragement, I am glad my post was helpful, hopefully you will find my upcoming post useful as well.
  With regards to your questions:
  1. Could you use concatenation to shorten the code? Probably, I haven’t tried it. Typically I tend to write things out longhand so to speak, as you see here each stage is clearly separated. This helps with understandability and maintainability.
  2. Using two processes once for the coverage model and another for the coverage collector, the important thing is to ensure all the collection bins are built at time zero, this happens when the process gets evaluated at time zero (All process run to their first wait). I am not sure of the benefit of splitting the coverage model into two parts.Maybe I will discuss this with Jim next time we speak
  
  Keep safe
  David…
David Clift wrote a new post 4 years, 6 months ago

There are many things that differentiate VHDL from Verilog. One example, is the ability to use global signals in Verilog, which enables a signal at the top-level to connect to one or more points in the hierarchy. […]
David Clift replied to the topic UCIS / UCDB in the forum OSVVM 4 years, 6 months ago

Hi Michael,

Thank you all of FirstEDA are working from home so we have been very busy for the last few months supporting our customers.

No CoverageApiPkg.vhd is NOT for Modelsim/Questasim it is just the place holder for the function calls that are needed to interface to a simulators coverage database. As far as I am aware Aldec is the only…[Read more]
David Clift replied to the topic UCIS / UCDB in the forum OSVVM 4 years, 6 months ago

This is certainly possible, OSVVM contains an API package (VendorCovApiPkg.vhd) this is a set of foreign procedures that link OSVVM’s CoveragePkg coverage model creation and coverage capture with the built-in capability of a simulator.
Aldec have created a version of this (VendorCovApiPkg_Aldec.vhdVendorCovApiPkg_Aldec.vhd) to work with their…[Read more]

David Clift

@dcfeda