There are many things that differentiate VHDL from Verilog. One example, is the ability to use global signals in Verilog, which enables a signal at the top-level to connect to one or more points in the hierarchy. […]
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No CoverageApiPkg.vhd is NOT for Modelsim/Questasim it is just the place holder for the function calls that are needed to interface to a simulators coverage database. As far as I am aware Aldec is the only…[Read more]
This is certainly possible, OSVVM contains an API package (VendorCovApiPkg.vhd) this is a set of foreign procedures that link OSVVM’s CoveragePkg coverage model creation and coverage capture with the built-in capability of a simulator.
Aldec have created a version of this (VendorCovApiPkg_Aldec.vhdVendorCovApiPkg_Aldec.vhd) to work with their…[Read more]