Jim Lewis

All of the OSVVM VC have test cases for each feature. For AxiStream, they are in the directory AXI4/AxiStream/TestCases.
The set these they way you are thinking, see TbStream_AxiTiming1.vhd and TbStream_AxiTiming2.vhd. You can also use random delays, see TbStream_SendGetRandom1.vhd and TbStream_SendGetRandom2.vhd

Below is what I see running XSIM using $OsvvmLibraries/RunAllTests.pro. There are 8 failures in the RunAllTests.pro. They all have to do with passing integer and time values through the transaction record. With time it never works. With integer, it seems to work some of the time. For integer it may be possible to trace the why, for time it…[Read more]

From the Scripts_user_guide.pdf:
To run OSVVM scripts in XSIM, start Vivado and then run the StartXSIM using:
source <path-to-OsvvmLibraries>/OsvvmLibraries/Scripts/StartXSIM.tcl

This will then set the simulator to XSIM and instead of analyzing MemoryGenericPkg.vhd, it will do:
analyze deprecated/MemoryGenericPkg_xilinx.vhd

All of the…[Read more]

These above write bin values were not generated by the code you posted. See annotations in the code.

Hi ALex,
I added the two suggestions I made previously to the code. Choose one of them.
I also changed the WaitForClock(clk, 2) to WaitForClock(InterruptRec, 2).
Usually I do not put clock in TestCtrl. The reason being is if you have lots of
different clocks in your system, it is easy to use the wrong one.

`
rx_process : process is…[Read more]

Hi Alex,
I see a delta cycle issue. Call ICover using Cnt rather than rx_cnt_s.
Or alternately do a wait for 0 ns ; before the call to ICover.

Best Reegards,
Jim

Hi Alex,
Please use a separate topic for separate issues.

I don’t see anything obvious in your code. Have you tried single step?

Jim

I have not seen Siemens HDL Designer Pro flow, so I cannot comment on how to use it. Like most things there may be a way.

Avalon MM is progressing slowly.

Hi Mickie
What version of Questa are you using?

With 2024.2 I turned on VHDL-2019. The features work fine, but in 2025.1 Questa decided to throw warnings for this feature.

If it is not 2025.1, then it is probably too old like 10.4 or 10.5.

I have been running regressions with 2024.3_1.

Best Regards
Jim

> Is there a possibilty to use any of the Modelsim/Questa simulator features for the OSVVM functional coverage reporting?

Not at this time. We looked at exporting an XML to UCIS, but they do not support the UCIS standard in this area. There is a C interface, but UCIS is based on crossing existing item/point coverage models using to create a…[Read more]

Hi Alex,
What is your motivating factor to use VUnit? Is there some capability there that you would like to see in OSVVM? Are you just using VUnit as a test runner or are you also using some of the VHDL code that is part of VUnit?

Currently OSVVM HTML reports are collaboration of OSVVM scripting and OSVVM VHDL code. The Test Case reports are…[Read more]

Hi Ajeetha,
I had started a reply right away and thought I had finished, but apparently forgot to submit it.

TCover in OSVVM is does transition coverage. You will need to name your something different.

It is ok to use the existing data structure for TCover to record the last value. I think your check is off a little as yours currently will…[Read more]

OSVVM supports 2 processes for interrupt handling. See https://github.com/OSVVM/Documentation/blob/main/InterruptHandler_user_guide.pdf for details.

It uses 2 separate records. Control flow automatically switches to the interrupt handling process when an interrupt is pending. As described in the user guide it requires a specific interrupt…[Read more]

Can you describe what you are doing.

While you can release the record there are other approaches.

For interrupt handling, OSVVM has an interrupt handler. See the common (MIT) repository in OsvvmLibraries.

You can also directly access OSVVM memories – no transaction record required

Out teaching OSVVM this week so it is harder to give…[Read more]

Hi Charles,
Currently OSVVM does not have control of where the Xilinx library goes. While we want it to go in the VHDL_LIBS directory, currently it is not.

Once we have control of where the library is, then to have two projects share the same compiled image of OsvvmLibraries we need to have a separate place for the OsvvmLibraries and the…[Read more]

I have pushed an update to the documentation on GitHub to clarify this issue. If you navigate from OsvvmLibraries navigate from the dev branch. If you navigate directory to Documenation repository – it is the most recent push.

A direct link to it is here: https://github.com/OSVVM/Documentation/blob/main/Axi4_VC_user_guide.pdf

Hi Alpha,
The Axi4Memory supports the full capability of the AXI4 bus from the DUT side interface – including a multi-beat burst. This allows the DUT to interact with any addressable location in the memory. Be careful to keep your address space reasonable as the Axi4Memory creates a data structure and sizes above 2**40 are not currently…[Read more]

Hi Brad,
Currently if you run things from VUnit, you loose all the OSVVM reporting. This is a direction we are currently investigating, but will either need to uplevel our tcl expertise or outside help.

How many different simulation sets do you intend to run? What I do normally is group my tests into test suites that test individual…[Read more]

Hi Steve,
While I think we have all of the OSVVM Utility library for Xcelium, I am not sure if Xcelium runs all of OSVVM VC test cases yet. I am not as good at Xcelium as other simulators. I would be willing to look at it with you and can setup a Zoom session if you like. I need to learn how to single step in Xcelium.

Do you know which…[Read more]