Jim Lewis
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Jim Lewis replied to the topic Support for Forcing DUT Signals via OSVVM in the forum OSVVM 2 weeks, 4 days ago
If the signals you want to drive are on an interface, then your verification component can be built so that it triggers all error conditions.
If the signals you want to drive are deep in your design, you can test that capability at the level where those signals are exposed.
Alternately if signals you want are deep in the design and you…[Read more]
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Jim Lewis replied to the topic Found Issue with numeric_std in the forum VHDL 1 month ago
Hi Ken,
VHDL Issues are logged here: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issuesPlease do a search before entering a bug as it may have already been found. I too have seen at least one issue – null strings are not handled according to 1076 rules.
Best Regards,
Jim -
Jim Lewis started the topic Job Post: VHDL Verification Engineer in the forum OSVVM 1 month, 3 weeks ago
Northrop Grumman in San Diego is looking for a Senior Principal Digital Verification Engineer. Many of the groups there are using OSVVM. See:
https://ngc.wd1.myworkdayjobs.com/Northrop_Grumman_External_Site/job/United-States-California-San-Diego/Senior-Principal-Digital-Verification-Engineer_R10169704 -
Jim Lewis started the topic What are the Xilinx Directories in the OSVVM release for? in the forum OSVVM 2 months ago
The Xilinx directories with test harnesses and/or test cases are for XSIM test and debug.
Hopefully these will go away after we get full support from XSIM.These do not apply to other simulators.
They are not special versions for Xilinx hardware. Use the regular versions for testing Xilinx hardware in other simulators.
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Jim Lewis replied to the topic vsimsa has no SetVHDLVersion 2019 in the forum OSVVM 2 months, 4 weeks ago
Oops. Will get that in shortly. Thanks for the observation
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Jim Lewis replied to the topic impore function GotScoreboards – Fatal: (SIGSEGV) Bad handle or reference. in the forum OSVVM 3 months, 1 week ago
Hi Cahit,
That is a bug in ModelSim 2016.04.In addition to that bug, you may run into scripting issues as the version of TCL is with 2016 is too old.
You will need a newer simulator version. Keep in mind that simulator is 8 years old at this point. They have fixed many bugs since then.
Best Regards,
Jim -
Jim Lewis replied to the topic Viewing wave during simulation run in the forum OSVVM 4 months ago
Hi Jeremy
For a simulation to run fast, a general strategy is to log wave forms (SetLogSignals) and display the waves after the simulation completes (DoWaves).If you want to run waves during the simulation, the following scripts are run (in this order) during simulate (called by simulate or by RunTest) if they exist:
– .tcl
– .tcl
-…[Read more] -
Jim Lewis replied to the topic Modify Pop Word to handle more than a Byte in the forum OSVVM 4 months, 1 week ago
Hi Jeremy
What are you trying to do? I think I am miss understanding something.The intent of PopWord is to pop a data’length sized word from a byte oriented FIFO and for the first word, adjust the number of bytes assembled in a coordinated fashion with the ByteAddress.
The pop (procedure and function) that is part of the Scoreboard/FIFO API…[Read more]
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Jim Lewis wrote a new post 4 months, 1 week ago
OSVVM Webinars and Classes Upcoming Webinars. August 15 Why Should Our Team be Using VHDL + OSVVM for Verification? EU and Early US Session: 7 am PDT / 10 am EDT / […]
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Jim Lewis started the topic CreateClock moved to ClockResetPkg in 2024.07 in the forum OSVVM 4 months, 2 weeks ago
In 2024.07, CreateClock (and CreateReset) moved from TbUtilPkg to ClockResetPkg. This was done to separate the dependencies that are needed from the low level synchronization primitives from the higher level CreateClock (and the checkers that check the clock period and reset).
If you had a reference to CreateClock using a selected name as…[Read more]
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Jim Lewis replied to the topic Error on running a script twice in the forum OSVVM 4 months, 2 weeks ago
Hi Preston,
What version are you running? Did the previous build fail?Prior to 2024.07, if an include failed, there were some conditions under which it would not restore the CurrentWorkingDirectory back to the original value. This was addressed in 2024.07. This only happened if something in the process used an exit code that indicated a…[Read more]
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Jim Lewis replied to the topic Convert std_logic_vector to record in the forum VHDL 4 months, 3 weeks ago
Yes it should have more regular updates. However to do that we need more volunteers and/or funding for the people who do the work.
Personally, I put in 1000+ hours of my own time into VHDL-2019. I cannot afford to do that amount of uncompensated time in the future.
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Jim Lewis replied to the topic Why does VHDL require explicit conversion from signed/unsigned to logic vector? in the forum VHDL 4 months, 3 weeks ago
Like types integer and real, the types signed, unsigned, and std_logic_vector are different types.
One really cool thing about different types is they support independent overloading, hence, the “+” operator for signed is unique and different from the “+” operator for unsigned. If they automatically converted this would not be possible.
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Jim Lewis wrote a new post 4 months, 3 weeks ago
OSVVM release 2024.07 + Conference Trip ReportIt seems like yesterday that I got back from Verification Futures Conference (June 18) and FPGA Conference Europe (July 2-4) – but it is actually been three […]
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Jim Lewis replied to the topic Does VHDL contain functions like Verilog $readmemb and $readmemh? in the forum VHDL 4 months, 4 weeks ago
Hi Hassan,
For the OSVVM MemoryPkg, see FileReadH and FileReadB as well as their counter parts FileWriteH and FileWriteB.For simulation based RAMS, you want to be using OSVVM’s MemoryPkg as it creates sparse memory data structures – ie it only allocates blocks of memory (in 1 K chunks) if you write to a particular location.
Best Regards,
Jim -
Jim Lewis replied to the topic Convert std_logic_vector to record in the forum VHDL 5 months ago
Hassan,
The way languages get enhanced is for people like yourself to go to the working group web page and make proposals and contribute to the development effort.For VHDL, the appropriate place to make proposals is at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/
VHDL in particular is a volunteer driven standard. Hence, it is…[Read more]
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Jim Lewis replied to the topic Creating Asynchronous Clocks in the forum OSVVM 5 months ago
2024.07 updates CreateClock. They are breaking changes – meaning the way clock starts up is different. There was alot of unneeded complexity that was part of the old CreateClock that has been minimized – while still keeping clock changing at simulation cycle 0 (aka delta cycle 0).
If you want to preview it, see the Dev branch. Nominally it…[Read more]
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Jim Lewis replied to the topic case splitting in the forum OSVVM 5 months ago
Just a quick note, release 2024.07 will have a CreateJitterClock:
`
procedure CreateJitterClock (
signal Clk : inout std_logic ;
signal CoverID : inout CoverageIdType ;
constant Name : in string ;
constant Period : in time ;
constant DutyCycle : in real := 0.5 ;…[Read more] -
Jim Lewis replied to the topic Mixed language simulation and synthesis support in the forum VHDL 5 months, 1 week ago
The IEEE group that works on EDA standards in general and spawns out groups like the IEEE 1076 WG is named DASC. You can find their website here: https://dasc.org/ You can certainly work through them to form such a working group.
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Jim Lewis replied to the topic VHDL Assert that prints the entity instance name and path in the forum VHDL 5 months, 1 week ago
You should be able to surround the process with
`– synthesis translate_off
process …
end process;
— synthesis translate_on - Load More