Jim Lewis

Oops. Will get that in shortly. Thanks for the observation

Hi Cahit,
That is a bug in ModelSim 2016.04.

In addition to that bug, you may run into scripting issues as the version of TCL is with 2016 is too old.

You will need a newer simulator version. Keep in mind that simulator is 8 years old at this point. They have fixed many bugs since then.

Best Regards,
Jim

Hi Jeremy
For a simulation to run fast, a general strategy is to log wave forms (SetLogSignals) and display the waves after the simulation completes (DoWaves).

If you want to run waves during the simulation, the following scripts are run (in this order) during simulate (called by simulate or by RunTest) if they exist:

– .tcl
– .tcl
-…[Read more]

Hi Jeremy
What are you trying to do? I think I am miss understanding something.

The intent of PopWord is to pop a data’length sized word from a byte oriented FIFO and for the first word, adjust the number of bytes assembled in a coordinated fashion with the ByteAddress.

The pop (procedure and function) that is part of the Scoreboard/FIFO API…[Read more]

Hi Preston,
What version are you running? Did the previous build fail?

Prior to 2024.07, if an include failed, there were some conditions under which it would not restore the CurrentWorkingDirectory back to the original value. This was addressed in 2024.07. This only happened if something in the process used an exit code that indicated a…[Read more]

Yes it should have more regular updates. However to do that we need more volunteers and/or funding for the people who do the work.

Personally, I put in 1000+ hours of my own time into VHDL-2019. I cannot afford to do that amount of uncompensated time in the future.

Like types integer and real, the types signed, unsigned, and std_logic_vector are different types.

One really cool thing about different types is they support independent overloading, hence, the “+” operator for signed is unique and different from the “+” operator for unsigned. If they automatically converted this would not be possible.

Hi Hassan,
For the OSVVM MemoryPkg, see FileReadH and FileReadB as well as their counter parts FileWriteH and FileWriteB.

For simulation based RAMS, you want to be using OSVVM’s MemoryPkg as it creates sparse memory data structures – ie it only allocates blocks of memory (in 1 K chunks) if you write to a particular location.

Best Regards,
Jim

Hassan,
The way languages get enhanced is for people like yourself to go to the working group web page and make proposals and contribute to the development effort.

For VHDL, the appropriate place to make proposals is at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/

VHDL in particular is a volunteer driven standard. Hence, it is…[Read more]

2024.07 updates CreateClock. They are breaking changes – meaning the way clock starts up is different. There was alot of unneeded complexity that was part of the old CreateClock that has been minimized – while still keeping clock changing at simulation cycle 0 (aka delta cycle 0).

If you want to preview it, see the Dev branch. Nominally it…[Read more]

Just a quick note, release 2024.07 will have a CreateJitterClock:

`
procedure CreateJitterClock (
signal Clk : inout std_logic ;
signal CoverID : inout CoverageIdType ;
constant Name : in string ;
constant Period : in time ;
constant DutyCycle : in real := 0.5 ;…[Read more]

The IEEE group that works on EDA standards in general and spawns out groups like the IEEE 1076 WG is named DASC. You can find their website here: https://dasc.org/ You can certainly work through them to form such a working group.

You should be able to surround the process with
`– synthesis translate_off
process …
end process;
— synthesis translate_on

Hi Lars,
OSVVM has an InterruptHandler.vhd in OsvvmLibraries/Common/Src. It handles switching records for you. When there is no interrupt pending, it connects the transaction record of TransRec to the AddressBus VC (such as Axi4Manager or Axi4LiteManager). When an interrupt is pending it connects the InterruptRec to the AddressBusVC.

The…[Read more]

Hi Hassan,
It is part of VHDL-2019. It is called Conditional Analysis. I have heard that vendors support it in older revisions.

For details, see my presentation, VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and Environment. I did this through Aldec as one of their events. You should be able to register…[Read more]

Hi Lars,
OSVVM has an InterruptHandler.vhd in OsvvmLibraries/Common/Src. It handles switching records for you. When there is no interrupt pending, it connects the transaction record of TransRec to the AddressBus VC (such as Axi4Manager or Axi4LiteManager). When an interrupt is pending it connects the InterruptRec to the AddressBusVC.

The…[Read more]

Hi Steve,
No documentation yet. Set the test case that is for now in TestStandAlone/Tb_xMii.vhd.

The VC are streaming interfaces that accept SendBurst and GetBurst.

Best Regards,
Jim