Jim Lewis

I have pushed an update to the documentation on GitHub to clarify this issue. If you navigate from OsvvmLibraries navigate from the dev branch. If you navigate directory to Documenation repository – it is the most recent push.

A direct link to it is here: https://github.com/OSVVM/Documentation/blob/main/Axi4_VC_user_guide.pdf

Hi Alpha,
The Axi4Memory supports the full capability of the AXI4 bus from the DUT side interface – including a multi-beat burst. This allows the DUT to interact with any addressable location in the memory. Be careful to keep your address space reasonable as the Axi4Memory creates a data structure and sizes above 2**40 are not currently…[Read more]

Hi Brad,
Currently if you run things from VUnit, you loose all the OSVVM reporting. This is a direction we are currently investigating, but will either need to uplevel our tcl expertise or outside help.

How many different simulation sets do you intend to run? What I do normally is group my tests into test suites that test individual…[Read more]

Hi Steve,
While I think we have all of the OSVVM Utility library for Xcelium, I am not sure if Xcelium runs all of OSVVM VC test cases yet. I am not as good at Xcelium as other simulators. I would be willing to look at it with you and can setup a Zoom session if you like. I need to learn how to single step in Xcelium.

Do you know which…[Read more]

Hi David,
There may be some things you could do now to create what you want. I would probably merge the YAML files and then look at how build finishes as that is the step where the code coverage is merged.

Best Regards,
Jim

Hi David,
Not yet. There are some planned changes coming later this year (2nd half) that should allow us to do this.

If you are thinking code coverage data, you should be able to merge the results from each build together using the tool provided methods. It would be easy to add that capability to OSVVM.

Where we currently have one big…[Read more]

Hi Steve,
rlwrap is not required. It provides a command line history – like bash does that you can move through with up and down arrows. There may be an alternative on newer OS’s. I am still running Centos 7.. I need to update to a newer version soon as this one only supports tcl 8.5 and OSVVM is happier with 8.6.

Best Regards,
Jim

If the signals you want to drive are on an interface, then your verification component can be built so that it triggers all error conditions.

If the signals you want to drive are deep in your design, you can test that capability at the level where those signals are exposed.

Alternately if signals you want are deep in the design and you…[Read more]

Hi Ken,
VHDL Issues are logged here: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues

Please do a search before entering a bug as it may have already been found. I too have seen at least one issue – null strings are not handled according to 1076 rules.

Best Regards,
Jim

Oops. Will get that in shortly. Thanks for the observation

Hi Cahit,
That is a bug in ModelSim 2016.04.

In addition to that bug, you may run into scripting issues as the version of TCL is with 2016 is too old.

You will need a newer simulator version. Keep in mind that simulator is 8 years old at this point. They have fixed many bugs since then.

Best Regards,
Jim

Hi Jeremy
For a simulation to run fast, a general strategy is to log wave forms (SetLogSignals) and display the waves after the simulation completes (DoWaves).

If you want to run waves during the simulation, the following scripts are run (in this order) during simulate (called by simulate or by RunTest) if they exist:

– .tcl
– .tcl
-…[Read more]

Hi Jeremy
What are you trying to do? I think I am miss understanding something.

The intent of PopWord is to pop a data’length sized word from a byte oriented FIFO and for the first word, adjust the number of bytes assembled in a coordinated fashion with the ByteAddress.

The pop (procedure and function) that is part of the Scoreboard/FIFO API…[Read more]

Hi Preston,
What version are you running? Did the previous build fail?

Prior to 2024.07, if an include failed, there were some conditions under which it would not restore the CurrentWorkingDirectory back to the original value. This was addressed in 2024.07. This only happened if something in the process used an exit code that indicated a…[Read more]

Yes it should have more regular updates. However to do that we need more volunteers and/or funding for the people who do the work.

Personally, I put in 1000+ hours of my own time into VHDL-2019. I cannot afford to do that amount of uncompensated time in the future.

Like types integer and real, the types signed, unsigned, and std_logic_vector are different types.

One really cool thing about different types is they support independent overloading, hence, the “+” operator for signed is unique and different from the “+” operator for unsigned. If they automatically converted this would not be possible.