Jim Lewis

Hi Michael,
One thing you can do is in your verification component create a setting that controls whether PRBS is to be inverted or not. Then use SetModelOptions to change the settings. For AxiStream we have numerous settings and use an abstraction layer on top of SetModelOptions called SetAxiStreamOptions. For AxiStream the abstraction…[Read more]

Please see GetRandPoint (its new name) in RandomPkg User Guide. There are also examples there.

Best Regards,
Jim

Hi Cols and Nico,
This brings up a bigger question, “how do we debug our simulations when something like this happens?”

First observe the time at which something happens. Look at what transactions were running before that time.

If our simulator supports interactive debugging such as single step and/or breakpoint, then the following may help…[Read more]

Hi Cols and Nico,
Did you look at TbAxi4_Shared1.vhd? Each instance of the VC needs to have its own record. See TestCtrl_e.vhd in the same directory.

Send me an email with your TestCtrl in it. It would probably be good to see your test harness also.

Best Regards,
Jim

Hi Gianico,
Each AxiStreamReceiver needs its own transaction record. In the OSVVM testcases, we are using a single record named StreamRxRec. You need separate ones, such as StreamRx1Rec and StreamRx2Rec.

There is an example of this done with the Axi4 interface. See directory OsvvmLibraries/AXI4/Axi4/testbench_MultipleMemory. In there see the…[Read more]

First, you are using the older, protected type based API. You might want to consider using the newer, singleton based API – it is simpler and does not require the test writer to use protected types (they are hidden internal to the singleton).

If you look at the document, OsvvmLibraries/Documentation/CoveragePkg_user_guide.pdf, you will find…[Read more]

I try to user either a Verification Component or a Monitor to provide an abstraction layer for all interactions with the DUT.

If there need to be exceptions to this, then you can use external names in TestCtrl to access items from the DUT. To make this feasible, when creating the test harness (top level netlist that connects DUT, VC, and…[Read more]

Hi Nico,
We don’t currently have anything to read that format, however, if I understood it right, it does not look too difficult to read.

What you want too look at with this sort of thing is how does the system interact with the image. For example, does the system receive the image via an AXI Stream interface? In this case you can have the…[Read more]

You should be able to use OSVVM with any QuestaSim version. Which version are you using? Are you having any problems? Have you run the OSVVM test suite and experienced any problems with QuestaSim?

I test with QuestaSim 2020.04. I have noticed some irregularities with some QuestaSim versions, but nothing that I could address by changing…[Read more]

Hi Steve,
I am just getting back to testing Cadence. Need to test with their Agile release. I think that may be a different release channel than normal, so I am trying to work through it.

Best Regards,
Jim

Hi Graeme,
You need to do build ../UART/testbench/testbench.pro

In OSVVM, build and include use a path reference relative to the script they are running.
Hence, in testbench.pro, it just says analyze TestCtrl_e.vhd. The path to testbench.pro gets
automatically prepended onto the file name. Hence, when writing scripts we only need to know
the…[Read more]

Hi Steve,
A quick update. I am working with Cadence on Xcelium. Things are looking up. I should have more news on this shortly.

I have provided them with the full OSVVM regression suite. I am optimistic, but I don’t know the time frame for them to update Xcelium.

A quick update. I am working with Synopsys on VCS. Things are looking up. I should have more news on this shortly.