Jim Lewis

Hi Adam,
Not yet. Are you interested in doing a pull request against TbUtilPkg?

Best Regards,
Jim

LibraryUnit in this case is the name which you used with simulate, hence, either the name of your testbench or configuration that runs your testbench. Often, I try to make this the same as the TextCaseName, but it does not have to be.

In VHDL, LibraryUnit is an analyzed Design Unit and from the LRM,

A design unit is
either an entity…

[Read more]

Hi Adam,
Currently the features that control these is described on pages 26 and 27 of the AxiStream_user_guide.pdf in OsvvmLibraries/Documentation. There are two controls for this:
RECEIVE_READY_BEFORE_VALID – this is true by default and allows TReady to be generated even if TValid is not asserted.
RECEIVE_READY_DELAY_CYCLES – Number of…[Read more]

Is that the Questa Intel edition or another edition?

Hi Anna,
Two thoughts on that.

First, there is no need for an expected SLVERR to be an actual test case error. The following is from p37 of the Axi4_VC_user_guide.pdf that is in the documentation repository:

By default, the expected value for BRESP and RRESP are OKAY. When testing a subordinates response to an incorrect address, a SLVERR is…[Read more]

Hi Oliver,
There is an OSVVM SPI model at: https://github.com/noasic/SPI

My long term plan is to clone it. It is a candidate for inclusion in OSVVM.

Best Regards,
Jim

Hi Antonio,
I did some testing with Synopsys over the last week.

It looks like when I added the error handling to the scripts, it broke the scripts for Synopsys. Unfortunately at the time I added the error handling to other aspects of the scripts, I did not have active Synopsys licenses.

I have updated the scripts now and they are working…[Read more]

Hi Michael,
Sorry I missed your post.

OSVVM pro scripts are a abstract procedure layer on top of TCL. Hence, you can do anything that TCL does. See the scripts OsvvmLibraries/OsvvmLibraries.pro and OsvvmLibraries/osvvm/osvvm.pro for examples.

Best Regards,
Jim

Hi Steve,
I did some testing with Cadence over the last week. Looks like the 2022.08 updates to memory pkg broke some things. On the dev branch of OSVVM, I moved MemoryPkg_c.vhd back to the 2022.06 version.

It also looks like Cadence is failing the singleton tests in CoveragePkg. I need to try to find root cause as the singleton tests in…[Read more]

Hi Oliver,
> Above all, there is no SystemVHDL as a complement to the SystemVerilog
Renaming Verilog to SystemVerilog is simply marketing. Just asking that question demonstrates the brilliance it.

OSVVM provides VHDL with “SystemVerilog + UVM” verification capabilities including Transaction Level Modeling, Constrained Random, Functional…[Read more]

Hi Thomas,
I try to divide the concerns into what must be done for every transaction and what is stable for a long period of time. Things that are stable for a long period of time can be set with SetModelOptions.

The error injection probability is a candidate for SetModelOptions.

You may wish for things like Image Width, Height, Color Depth,…[Read more]

Memory leak. I do not think the simulators are able to handle this for you.

I should note general VHDL questions like this may get a response faster on StackOverflow, however, I have indeed encountered this one and know a couple of solutions.

The simplest that I have seen, but not used (so it may have flaws) is:

`vhdl
function my_function(obj…[Read more]

Hi Anna,
Sorry, some how while answering your questions on GitHub, I missed your question here.

For all others, here is a summary of the resolution of Anna’s question.

With the 2022.10 update, the same actions can be accomplished with the following call to simulate. Note while the items in square brackets are optional, if you use generic…[Read more]