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VHDL-2017 – Time to Ballot …

February 24, 2017 in VHDL in general

The IEEE P1076 VHDL Standards Working Group has been busy preparing VHDL-2017. It is almost ready. As we are wrapping up, it is time for the VHDL community to prepare to ballot (aka vote). Balloting on the standard will be done some time between May and July.

If you are a member of the VHDL community, it is time to get ready to vote.

Voting is done through IEEE. Directions are below. You have until March 15 to enroll in the ballot pool.

Best Regards,
Jim Lewis
IEEE P1076 WG Chair


The IEEE Computer Society invites you to participate in the ballot for:

IEEE 1076: Standard for VHDL Language Reference Manual


If you are not an IEEE SA Member:

You can either enroll in a single ballot by paying a per ballot fee or you can join the IEEE SA by choosing an option link below. Joining the IEEE SA entitles you to participate in as many sponsor ballots as you like for the year.

OPTION 1 – I am already an IEEE Member and I want to add Standards Association Membership. Go to:

OPTION 2 – I am not an IEEE Member but would like to enroll in both IEEE and IEEE Standards Association. Go to:

OPTION 3 – I am not interested in becoming an IEEE Member, however I would like to enroll as a Standards Association Member only. Go to:

If you are an IEEE-SA member:

Go directly to:

Or, follow this process:

1. Log onto myProject; click the link for myBallot.

2. Click the link for myBallot (if applicable); click the link for “Show/Join Open Ballot Invitations”:

3. Scroll down until you find the open ballot group of interest to you; then scroll over to the right margin and click “join” under the “Actions” column.

4. Enter or select an affiliation from the drop down menu (appearing as you key in your affiliation in the Organization window), select your classification category, and click “OK” at the bottom of the screen. You will receive an on-screen confirmation that you successfully joined the group.




Balloting group members have an obligation to respond during the balloting period; failure to return a ballot may disqualify the balloter from participation in future balloting groups.

Once the document is ready to be balloted, you will receive notification via email. You will typically have 30 days to review the document and return the ballot with your vote. By agreeing to participate in this ballot you have an *obligation* to respond. Failure to return a completed ballot may disqualify you from participating in future ballots.

Thank you for your interest in this ballot.

IP Encryption (P1735) and VHDL

March 26, 2013 in VHDL in general

Currently the IEEE P1076 Working group is reviewing a draft of the proposed IP Encryption (P1735) and accessing how it maps into the pragmas created in VHDL-2008.

If you are developing and/or selling VHDL IP that you want to encrypt, you should be participating in this. More details at:

To participate, contact Jim at

VHDL Needs Your Help!

January 9, 2013 in VHDL in general

Dear OS-VVM Members and Readers!

VHDL needs your help. Since the publication of 2008 revision of VHDL Standard (IEEE Std 1076-2008), pretty decent amount of suggestions how to improve the language was accumulated. Now they have to be sorted, reviewed and turned into more formal requests. Anybody familiar with VHDL and willing to spend some time working on the new version of the standard is strongly encouraged to visit TWiki website:

You can snoop around without registering, but if you want to do some serious work you should contact Jim Lewis to get registered – details are in the “Participating” section.


Good luck in New Year!


Your Friendly Admin.

What’s In The Numbers?

December 21, 2012 in VHDL in general

We have recently experienced quite a few number-related events: (supposedly) magical 2012-12-12, (failed) End of the World due to today’s date in Mayan calendar (, etc. Since number handling is important in randomization and functional coverage – the heart of OSVVM – let’s talk about numbers in VHDL.

Numeric Types

VHDL gives us 3 kinds of numeric types: integer, physical and floating-point.

Integer types represent integral numbers from any convenient range. All ranges within –2147483647 and +2147483647 bounds must be supported, which means that 32-bit representation is required. To ensure fast processing of integer types, all modern VHDL simulators support their 32-bit, 2’s-complement internal representation.

The only predefined integer type is called INTEGER and must cover the aforementioned [–2147483647 .. +2147483647] range. Please note that it leaves out precisely one number that can be represented on 32 bits: –2147483648 decimal  (16#8000_0000# – that’s hexadecimal in VHDL). Many simulators have special option that allows extending INTEGER type by this solitary number, which lets you avoid some computational problems.

Physical types let you specify base unit and secondary units that are integral multiplicities of base unit. The best example of physical type is the only predefined physical type TIME. Let’s have a look at its declaration:

    type TIME is range −9223372036854775807 to 9223372036854775807
            fs;            −− femtosecond
            ps = 1000 fs;  −− picosecond
            ns = 1000 ps;  −− nanosecond
            us = 1000 ns;  −− microsecond
            ms = 1000 us;  −− millisecond
            sec = 1000 ms; −− second
            min = 60 sec;  −− minute
            hr = 60 min;   −− hour
        end units;

Please note that to cover all time units from femtosecond to hour, 32-bit representation is not enough. That’s why VHDL simulators settle on 64-bit time representation, as you may guess by looking at the declaration above. While other languages and even some simulators may be lenient here, VHDL syntax requires space between time numeric value and unit: “10 ns” is correct, but “10ns” is not.

Since 1 hour is 3.6*1018 femtoseconds, with full 1 fs precision you can only express time values up to slightly over 2 hours. If you reduce precision of time in your simulation tool, maximal time value you can express will increase accordingly. Let’s be honest: who needs precision below 1 picosecond in practical applications?

Floating-point types let you approximate real numbers by specifying signed integer part of the number followed by dot and fractional part of the number, e.g. “1.234” or “1.0” (this is floating-point one – “1” is integer one). Optionally you can specify ‘E’ character and signed, integer exponent after the fractional part, e.g. “31.415926E-1” or “1.0E6” (again, this is floating-point million – “1E6” is integer million).

The only predefined floating-point type is REAL, with range and precision depending on the host machine of the simulator. The rules of IEEE 754 standard must be followed in implementation of REAL type.

Array Based Types

For numeric applications that require specific hardware representation, VHDL coders can use popular bit or std_logic based array types: BIT_VECTOR, STD_LOGIC_VECTOR, SIGNED, UNSIGNED. Their main benefit is that they do not impose any significant size restrictions found in INTEGER.

VHDL 2008 introduced packages that provide unified, array-based representation of fixed-point and floating-point values. It is unique feature, highly appreciated in DSP community. Detailed description of those new types goes far beyond the scope of this post – please let us know if you need additional info.

Happy Holidays!

– Your Friendly Admin

Let’s Meet At DAC…

May 16, 2012 in Event, OS-VVM in general, VHDL in general

Semi-formal meeting of OS-VVM fans and VHDL users will be held at the 49th Digital Automation Conference (DAC 2012). The conference is located in San Francisco, California, USA this year. The entry to the exhibit hall at Moscone Center is free on Monday, June 4th – drop in if you happen to be in the area.

We are meeting at the ALDEC booth (#2126) at 2pm. To help us estimate how many visitors can appear, please reply to the forum post or use Contact Us form.

See you in San Francisco!

The (not so) Good Old Stuff

April 13, 2012 in VHDL in general

Good Day, VHDL Coders,

Many VHDL users who spent some time with the language automatically add use.std_logic_unsigned.all in front of all entities they create. It seems such a good idea when you work in your preferred workflow with just one simulator and synthesizer: one line of code and you can add and subtract standard logic vectors! Unfortunately, this package (and related ones coming from the same source) can be the source of serious problems, as any seasoned instructor, consultant or person who worked on standards can tell you. Let’s see why…

When Synopsys released a couple of packages (std_logic_arith, std_logic_signed and std_logic_unsigned) in early 1990′s they were a revelation, because they addressed a couple of shortcomings of the original VHDL-87 standard. They were also free (open source) so end-users did not have to pay IEEE to use them. But that’s the end of the list of advantages.

  1. Those packages were never (and still are not) a part of any VHDL standard, so they do not follow rules of newer VHDL versions and the standard itself ignore their contents.
  2. Since the packages are open source, many versions with subtle differences can be found, so you can be seriously surprised when you move your code from tool A to tool B.
  3. Set of implemented arithmetic operations is incomplete and conversion functions are poorly named and inconsistently implemented.
  4. They are absolutely incompatible with VHDL-2008.

Users of OS-VVM should be mainly concerned with issue number 4. Let’s analyze it.

VHDL-2008 folded standard logic types from 1164 standard into the main 1076 standard and simplified structure of vector types by making std_logic_vector subtype of std_ulogic_vector. As the result, creators of universal packages have to create only one version of subprograms dealing with vectors – the one supporting std_ulogic_vector. The new standard also added package numeric_std_unsigned that implements arithmetic operations and conversions on standard logic vectors in consistent and safe way; it should be the only package used if you compile your design in 2008 mode and plan to do arithmetic on std_logic_vector objects.

If your simulator has precompiled std_logic_unsigned package, it was almost certainly compiled in 2002 mode (or ’93 mode), so it relies on the old hierarchy of vector types where std_logic_vector is not a subtype of std_ulogic_vector. If you compile your design in 2008 mode to enable OS-VVM library and force the use of std_logic_unsigned at the same time, expect trouble: the confusion of expected and actually available types in system packages will lead to some problems.

Long story short, after 20 years it is time to forget old Synopsys packages. The new standard has numeric_bit, numeric_std, numeric_bit_unsigned and numeric_std_unsigned that do the same things much better.

Happy coding,

Your Admin.

Posting VHDL code in blog or forum

April 10, 2012 in Internet, VHDL in general

Posting plain text in the blog or forum should not be a problem to anybody who can type – no knowledge of programming languages is necessary. If, however, somebody wants to post a snippet of VHDL code, situation changes dramatically…

  1. First, the poster has to know what format is expected: plain text, rich text, HTML?
  2. Then the plain VHDL code must be converted to proper format (with exception of expected plain text format).
  3. Finally, converted VHDL must be pasted in the blog/forum editor.

Here’s how it looks on our website:

For blog posts/comments

We have installed rich text editor plugin, so the situation should be simple:

  1. For quick post, just copy VHDL code from your favorite editor to the blog editor.
  2. To make the code snippet look more like in the real code editor, select it and click toolbar button marked “Code snippet” (the button looks like this “#_“).
  3. If you have time and patience, you may select individual keywords and make them bold (or change their color).

That’s it!

For forum topics and replies

For now, restricted HTML is the only allowed format for majority of members. [See comment #2 for good news!]

  1. The use of “<code>…</code>” tag pair around the code snippet should help, but there are two more issues:
  2. Four characters play special role in HTML: ‘<’, ‘>’, ‘&’ and ‘”‘ (double-quote), so they should be replaced with special entity names: &lt;, &gt;, &amp;, &quot; (semicolon is the part of entity name, comma is not).
  3. Forum editor parser removes leading spaces and tabulations, so to maintain nice indentation you have to use non-breaking spaces that have the following entity name: &nbsp;.

The first step is easy: I recommend typing <code> in a new line, hitting Enter twice and typing </code> before pasting code snippet in the empty line between two tags.
The second step can be done manually via Search&Replace; be careful with ‘&’ representing concatenation in VHDL – you should replace it with some rare string, deal with other symbols and then replace rare string with &amp;.
If it seams too difficult, try excellent free editor Notepad++ in which TextFX | TextFX Convert | Encode HTML menu option will do all those replacements in the selected text in one step.
The third step can be done in any text editor; first replace all tabulations with proper number of non-breaking spaces (most frequently 4: &nbsp;&nbsp;&nbsp;&nbsp;) and then replace plain spaces with non-breaking ones.

While good programmer editors may have option to export your code directly to HTML, usually they will not do space/tab replacement.

The rules presented above should work for everybody. If you have better, revolutionary ideas, let us know in the comments to this post.

Happy coding,

Your Admin.