OSVVM: Making VHDL Transaction Based Testbenches Simple, Readable, Powerful, and Fun

June 6, 2017 in OS-VVM in general, Transaction Based Testbench

Just because your design is complex does not mean your testbench needs to be. In OSVVM we have found that with proper abstractions we can create simple, readable, and powerful testbenches.

In OSVVM 2016.11 we released the transaction based modeling approach we have been using for the past 20 years in our verification practice and classes. Looking at its block diagram, you will notice that its architecture looks similar to SystemVerilog + UVM.

Just like SystemVerilog, the OSVVM approach has a top-level sequencer, here named TestCtrl; it has verification models, CpuModel, UartTx, UartRx, and Memory; it has a top level testbench, sometimes called a test harness, named TbMemIO; and finally it has connections between the test sequencer and the models which we implement with OSVVM interfaces.

All of the models (TestCtrl, CpuModel, UartTx, UartRx) in the OSVVM environment are typically implemented with an entity and architecture. The coding of these models can be either behavioral or RTL-like. Generally this means that the models written by the testbench team are easily read by the RTL design team. It also means the RTL team can write testbench models.

An architecture of the top-level sequencer, TestCtrl, typically captures one test of the test suite. This allows the entire test to be viewed in one place. This is accomplished by using a separate process to sequence each interface of the DUT and utilizing OSVVM synchronization primitives (released in 2016.11) to coordinate activities in separate processes when necessary.

The final piece of the puzzle is OSVVM interfaces. An OSVVM Interface connects TestCtrl to a transaction based model. Each model has it own separate connection to TestCtrl. Since an OSVVM Interface is inout of both models, it is created using a record whose elements use the resolution function resolved_max from the OSVVM package ResolutionPkg. Using OSVVM Interfaces provides a simple migration path to VHDL-2017 Interfaces.

Just like SystemVerilog + UVM, OSVVM offers a complete VHDL verification methodology from transaction based testbenches, to functional coverage and randomized test generation, to scoreboards and memory modeling, to error reporting and verbosity control, and to basic utilities (process synchronization).

Ready to go the next step in your VHDL testbenches? Join me at one of the upcoming Advanced VHDL Testbenches and Verification classes. This class is a 5 day investment in time. Expect to gain deep knowledge in the application of OSVVM to ASIC and FPGA verification.

June 12 – 16 and June 26 – 29 on-line Enroll with SynthWorks
May 30 -June 2 and June 12-16 Web Class Enroll with SynthWorks
July 17-21 Freiburg, Germany Enroll with PLC2
July 31 – Aug 4 and Aug 14 – 18 on-line Enroll with SynthWorks
Aug 28 – Sept 1 and Sept 11 – 15 on-line Enroll with SynthWorks
September 25 – 29 Copenhagen, DK Enroll with FirstEDA

 

For our complete schedule see: http://synthworks.com/public_vhdl_courses.htm

If you liked this post and have an extra moment, please like the corresponding linkedin post at:
https://www.linkedin.com/pulse/osvvm-making-vhdl-transaction-based-testbenches-simple-jim-lewis

OSVVM: ASIC Level VHDL Verification To UK and Beyond!

April 10, 2017 in Event, OS-VVM in general

I am getting ready for the next session of Advanced Testbenches and Verification in UK and am looking forward to meeting another group of students.

Ready to improve your VHDL verification methodology?   Come join me, Jim Lewis, the OSVVM chief architect, for the class, Advanced VHDL Testbenches and Verification, and learn OSVVM step by step.

If you want to learn what is in OSVVM, you can read the manual.  However, if you want to learn OSVVM in depth, get the why’s behind the features, and be more productive sooner, then you will be best served by joining us.

Our next class dates are:

May 22-26 Bracknell, UK Enroll with FirstEDA
May 30 -June 2 and June 12-16 Web Class Enroll with SynthWorks
July 17-21 Freiburg, Germany Enroll with PLC2

 

OSVVM is a complete ASIC level VHDL Verification methodology that is simple and effective for ASIC or FPGA projects of any size.   This class is a 5 day investment in time.  Our goal is that after this class you will:

  • Create a structured test environment using either transaction level models (aka verification components) or procedures (aka BFMs).
  • Use procedures to initiate interface actions (such as CpuRead, CpuWrite, …)
  • Write transaction based tests that are readable by the entire community – including RTL, system, and software engineers
  • Utilize a test strategy, such as directed, algorithmic, constrained random, Intelligent CoverageTM random, or a mix of these that is appropriate and effective for a particular test
  • Use records and OSVVM resolution functions to create simple interfaces
  • Write functional coverage to track the completion of your test plan
  • Synchronize tests using OSVVM synchronization utilities
  • Simplify error reporting using OSVVM alerts and affirmations
  • Create messages for debug and test reports using OSVVM logs and affirmations
  • Use the OSVVM generic scoreboard for self-checking
  • Use the OSVVM memory package to create memory models
  • Write a test plan that maximizes reuse throughout the entire test process.
  • Accelerate the testing process
  • Save enough time (particularly if you were not previously using these techniques) to recoup the time you invested in training on each project

Don’t be stuck doing verification the time consuming, tedious way.   It is time to simplify and expedite your verification effort using OSVVM and make your testbenches both readable and fun.

This is an interactive class – we entertain verification questions and discussions both during and after class.

VHDL-2017 – Time to Ballot …

February 24, 2017 in VHDL in general

The IEEE P1076 VHDL Standards Working Group has been busy preparing VHDL-2017. It is almost ready. As we are wrapping up, it is time for the VHDL community to prepare to ballot (aka vote). Balloting on the standard will be done some time between May and July.

If you are a member of the VHDL community, it is time to get ready to vote.

Voting is done through IEEE. Directions are below. You have until March 15 to enroll in the ballot pool.

Best Regards,
Jim Lewis
IEEE P1076 WG Chair

***** IEEE STANDARD DOCUMENT INFORMATION *****

The IEEE Computer Society invites you to participate in the ballot for:

IEEE 1076: Standard for VHDL Language Reference Manual

***** ENROLLMENT INSTRUCTIONS *****

If you are not an IEEE SA Member:

You can either enroll in a single ballot by paying a per ballot fee or you can join the IEEE SA by choosing an option link below. Joining the IEEE SA entitles you to participate in as many sponsor ballots as you like for the year.

OPTION 1 – I am already an IEEE Member and I want to add Standards Association Membership. Go to: http://www.ieee.org/membership_services/index.html

OPTION 2 – I am not an IEEE Member but would like to enroll in both IEEE and IEEE Standards Association. Go to: http://www.ieee.org/membership_services/membership/join/index.html

OPTION 3 – I am not interested in becoming an IEEE Member, however I would like to enroll as a Standards Association Member only. Go to: http://standards.ieee.org/sa-mem/join.html

If you are an IEEE-SA member:

Go directly to:

https://development.standards.ieee.org/my-site/open-ballot-invitations

Or, follow this process:

1. Log onto myProject; click the link for myBallot.

2. Click the link for myBallot (if applicable); click the link for “Show/Join Open Ballot Invitations”: https://development.standards.ieee.org/my-site/open-ballot-invitations

3. Scroll down until you find the open ballot group of interest to you; then scroll over to the right margin and click “join” under the “Actions” column.

4. Enter or select an affiliation from the drop down menu (appearing as you key in your affiliation in the Organization window), select your classification category, and click “OK” at the bottom of the screen. You will receive an on-screen confirmation that you successfully joined the group.

============================================

OBLIGATIONS AND RESPONSIBILITIES OF BALLOTERS

============================================

Balloting group members have an obligation to respond during the balloting period; failure to return a ballot may disqualify the balloter from participation in future balloting groups.

Once the document is ready to be balloted, you will receive notification via email. You will typically have 30 days to review the document and return the ballot with your vote. By agreeing to participate in this ballot you have an *obligation* to respond. Failure to return a completed ballot may disqualify you from participating in future ballots.

Thank you for your interest in this ballot.

Announcing OSVVM™ 2016.11a

December 16, 2016 in Announcement, OS-VVM in general

2016.11a is a minor release. The only file that changed is VendorCovApiPkg_Aldec.vhd. There was a bug in one of the attributes that has been fixed and verified.

VendorCovApiPKg simplifies the connection between OSVVM functional coverage a vendor’s internal functional coverage database. The operation of the API is simple. Within OSVVM, all calls to create a functional coverage model (AddBins and AddCross) and record coverage (ICover) are forwarded to a simulator via VendorCovApiPkg. The simulator can use these calls to create an internal version of the functional coverage model and record the coverage.

VendorCovApiPkg_Aldec.vhd works with Riviera-PRO 2016.10. Aldec anticipates that the next release of Active-HDL will support VendorCovApiPkg_Aldec.vhd.

The heart of VendorCovApiPkg is covered in two pages of VendorCovApiPkg_user_guide.pdf.

OSVVM Webinar December 15 and Classes

December 13, 2016 in Announcement, Event, OS-VVM in general

Webinar From OSVVM to UCIS Database. Thursday December 15, 2016

When a simulator records functional coverage internally, it gains the ability to correlate the functional coverage with its verification planning tools and share that information with safety critical tools.

The 2016.11 release of Open Source VHDL Verification Methodology (OSVVM) adds an API to record OSVVM Functional Coverage directly into a simulator’s UCIS database.

This task has been on our todo list for quite some time. UCIS is complicated. Fortunately the engineers at Aldec were up to creating an initial implementation. Together we revised it.

Join OSVVM architect and VHDL trainer, Jim Lewis, and Aldec Software Product Manager, Radek Nawrot, for a presentation and demonstration of how to add this capability to your VHDL testbench.

Europe Session 3-4 pm CET 6-7 am PST 9-10 am EST Enroll with Aldec
US Session 11 am -12 noon PST 2-3 pm EST 8-9 pm CET Enroll with Aldec

OSVVM World Tour Training Dates

VHDL Testbenches and Verification – OSVVM+ Boot Camp

Learn the latest VHDL verification techniques including transaction level modeling (tlm), self-checking, scoreboards, memory modeling, functional coverage, directed, algorithmic, constrained random, and intelligent testbench test generation. Create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog or ‘e’. Our techniques work on VHDL simulators without additional licenses and are accessible to RTL engineers.

January 16-20 and January 30-February 3 Web Class Enroll with SynthWorks
February 20-25 Freiburg, Germany Enroll with PLC2
March 6-10 Nordic Region Enroll with FirstEDA
March 13-17 and March 27-31 Web Class Enroll with SynthWorks
April 17-21 and May 1-5 Web Class Enroll with SynthWorks
May 8-12 Freiburg, Germany Enroll with PLC2
May 22-26 Bracknell, UK Enroll with FirstEDA

Announcing OSVVM™ 2016.11

December 9, 2016 in Announcement, OS-VVM in general

New Capability Summary

  • Link OSVVM Functional Coverage to a simulator’s UCIS database
  • Data checking using scoreboards
  • Transaction interfaces using records
  • Testbench synchronization utility

This adds the packages VendorCovApiPkg, ScoreboardGenericPkg, TbUtilPkg, and ResolutionPkg.

Link OSVVM Functional Coverage to a Simulator’s UCIS Database

When a simulator records functional coverage it gains the ability the ability to correlate the functional coverage with its verification planning tools and share that information with safety critical tools.

The 2016.11 release adds an API to record OSVVM Functional Coverage a simulator’s UCIS database.

This task has been on our todo list for quite some time.   UCIS is complicated.   Fortunately the engineers at Aldec were up to creating an initial implementation.  Together we revised it.   Currently there are two packages in OSVVM:  VendorCovApiPkg.vhd (a nominal implementation which leaves OSVVM and the simulator disconnected) and VendorCovApiPkg_Aldec.vhd (which connects OSVVM Functional Coverage to Aldec simulators).

The operation of the API is simple. Within OSVVM, all calls to create a functional coverage model (AddBins and AddCross) and record coverage (ICover) are forwarded to a simulator via VendorCovApiPkg. The simulator can use these calls to create an internal version of the functional coverage model and record the coverage.

Now that we have an implementation pattern I look forward to working with other simulator vendors to integrate in their tools.  The heart of VendorCovApiPkg is covered in two pages of VendorCovApiPkg_user_guide.pdf.

I will be doing a webinar on December 15 titled, “From OSVVM VHDL Functional Coverage to UCIS-based database” with Aldec.   An announcement will follow shortly.

Data Checking Using Scoreboards

A scoreboard is a data structure used to simplify self-checking in an environment where inputs are closely related to outputs, such as in data transmission (serial ports, networking, …).   Scoreboards are particularly useful when data transmission has latency between the source and destination of the information.

I will be doing a more detailed blog on scoreboards at a later date.   For now you can consult the ScoreboardPkg_user_guide.pdf

Transaction Interfaces Using Records

Currently a record is the only VHDL abstraction that groups different types together.   The problem is, how, do we create a bidirectional transaction interface using records.    Do we use one record as inout or separate records for each direction of communication?

The OSVVM methodology is to use a single record whose elements use a resolution function that is defined in ResolutionPkg.   ResolutionPkg defines resolution functions and subtypes that apply the resolution functions to common VHDL types. The 2016.11 implementation of ResolutionPkg takes a step forward by introducing “maximum” style resolution functions that work well with the VHDL default initialization of type’left (and do not require any other initialization – such as would be required if you used std_logic or std_logic_vector).

I will be doing a more detailed blog on using records for transaction interfaces at a later date. For now you can consult ResolutionPkg_user_guide.pdf.

Testbench Synchronization Utility

To further simplify transaction level modeling, SynthWorks’ has released its TbUtilPkg into OSVVM.   This package provides synchronization and handshaking utilities for transaction interfaces and independently running processes.

I will be doing a more detailed blog on transaction and process syncrhonization at a later date.   For now you can consult TbUtilPkg_user_guide.pdf.

What is Really New?

ScoreboardPkg, ResolutionPkg, and TbUtilPkg have been used in SynthWorks’ classes for quite some time now. For students in our classes, these packages represent the latest evolutionary refinement of our methodology. To me, even though they had yet to be released in OSVVM, I have always considered these to be a fundamental part of the OSVVM methodology.

OSVVM™ Boot Camp

SynthWorks primary business is training. Our class, Advanced VHDL Testbenches and Verification – OSVVM™ Boot Camp will bring your team up to speed on using OSVVM. Follow this link to our current class schedule.

Getting the release

OSVVM release 2016.11 is available as a zip at OSVVM Downloads.

OSVVM release 2016.11 is available via git at OSVVM GitHub. Note the repository just moved to an organizational account so if you are already linking to the OSVVM github, be sure to update to the new links (the old ones will work for a short amount of time).

Spammers and Hackers, … Oh My

April 29, 2016 in Announcement

Yesterday myself and numerous others (perhaps all) received an email from Esther and Love via the OSVVM website. The email was generated by an account that they had. When I see something like this, I delete the account – which is exactly what I did yesterday.

I suspect these accounts were created using the normal channel of enrollment and not a hack (as they did nothing else damaging). We are looking into updating the account sign in process to make sure this does not happen again.

Jim

OSVVM on Aldec, Mentor, GHDL, and working towards Cadence

February 20, 2016 in OS-VVM in general

OSVVM 2016.01 Tested On
Some may think that OSVVM only works on a particular simulator. Not so. I test OSVVM on the latest release of Aldec ActiveHDL, Aldec RivieraPro, Mentor QuestaSim, and GHDL that I have installed. 2016.01 was tested and passes all regressions on:
Aldec ActiveHDL 10.2
Aldec RivieraPro 2015.02
Mentor QuestaSim 10.4d
GHDL 0.33

Beyond OSVVM 2016.01
Any minor bugs that are found will be fixed on the GitHub site first. To get the latest see: https://github.com/JimLewis/OSVVM

Working Towards Cadence
OSVVM is for all simulators. So for any simulator for which people report bugs, I will try to create work arounds.

On that theme, we have a number of people who have been reporting issues with Cadence simulators. As a result, I have created a Dev_Cadence branch to work around as many of the issues encountered by Cadence simulators as possible. So far I have fixes for everything that I have seen recorded. Sometimes this may mean reduced capability. But nothing of any significance yet.

See Dev_Cadence.md for the list of changes. A direct link to the Dev_Cadence branch is here: https://github.com/JimLewis/OSVVM/tree/Dev_Cadence

I do not have a copy of the Cadence tools at this time, so please let me know the next set of issues you encounter, and I will get them incorporated into the branch. You can directly email me at jim at synthworks dot com. You can also message me through osvvm.org. You can submit issues against the branch on GitHub (preferred as it is easier for me to track and close).

OSVVM on GitHub, OSVVM Training in Germany, and other OSVVM Training Datess

February 10, 2016 in Announcement, Event, OS-VVM in general

OSVVM on GitHub
OSVVM is now on GitHub. You can find releases there. I will be putting bug patches there first before formally releasing them on OSVVM.org. Long term I also plan on putting tool specific branches as needed (such as for Cadence).

https://github.com/JimLewis/OSVVM

OSVVM Training in Germany
In conjunction with PLC2, we will be offering OSVVM training in Germany. See the matrix below for the first two dates in Freiburg, Germany.

OSVVM Training Dates
VHDL Testbenches and Verification – OSVVM+ Boot Camp
Learn the latest VHDL verification techniques including transaction level modeling (tlm), self-checking, scoreboards, memory modeling, functional coverage, directed, algorithmic, constrained random, and intelligent testbench test generation. Create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog or ‘e’. Our techniques work on VHDL simulators without additional licenses and are accessible to RTL engineers.

February 29 – March 4 Freiburg, Germany Enroll with PLC2
March 28 – April 1 and April 11-15 online class Enroll with SynthWorks
April 25-29 Stockholm, Sweden Enroll with FirstEDA
May 9-13 Freiburg, Germany Enroll with PLC2
May 23-27 and June 13-17 online class Enroll with SynthWorks
July 25-29 and August 8-12 online class Enroll with SynthWorks
September 12-16 Bracknell, UK Enroll with FirstEDA

Announcing OSVVM™ release 2016.01

January 26, 2016 in Announcement, OS-VVM in general

2016.01
Fixed a bug in AlertLogPkg that kept more than 32 AlertLogIDs from being used.
Updated CoveragePkg, MemoryPkg, and TextUtilPkg for GHDL (function purity and indexing objects of type line)

2015.06 (released previously, but not announced)
Added MemoryPkg to easily implement sparse data structures used in memory models.
In AlertLogPkg, added AffirmIf, added PASSED log level.
In CoveragePkg, implemented mirroring for WriteBin and WriteCovHoles