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I wonder if / why Xilinx doesn’t support VHDL anymore:
In the Feb 16, 2023 Xilinx document 63988 – “How to run timing simulation using Vivado Simulator?” it is stated: “There is no support for VHDL timing simulation.”
And in the Feb 16, 2023 Xilinx article “Simulating AXI interfaces with the AXI Verification IP (AXI VIP)” it says that “All of the…[Read more]

I’m looking to create a simulation that uses two asynchronous clocks, is there a way within OSVVM to add a delay before starting a clock so that it does not begin generating at time 0 in a simulation?

I’m not seeing any options for this within the CreateClock procedure, is there possibly another function that allows this behavior?

Thanks.