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Was there any reaction of Siemens? I wonder who is working there at Questa anyway – i suggest these are the former Mentor programmers?

I have the same issue here, but only newer Questa. Formerly i did not recognize this. Possibly a config issue.

My question would be what the intention is in detail: Typically sensor interfaces are simulated and tested independently from the image content. Therefore I produced a test package capeable of driving various signal schemes and bahaviour into the lvds lines which can be simulated and also synthesized into an FPGA for real investigations of eye…[Read more]

I still do not like the ambigious way, vectors are treated agains signals, and that there is conversion required in between a(0 downto 0) = “1” instead of using “a(0) = ‘1’). See the bram addressing regarding their write enable. This is one signal only, however one uses 0…0 instead of a signal. So VHDL could be made more tolerant for that.

Hi Oliver,
There is an OSVVM SPI model at: https://github.com/noasic/SPI

My long term plan is to clone it. It is a candidate for inclusion in OSVVM.

Best Regards,
Jim

Hi Jim,

thank you for the detailed answers!

Actually I’m looking at the PCIe test framework from Xilinx. The AXI I’m planning to verify is already included in OSVVM, as I could see. For QSPI as another task I will probably need to write my own.

Best regards
Oliver

Hi Antonio,
I did some testing with Synopsys over the last week.

It looks like when I added the error handling to the scripts, it broke the scripts for Synopsys. Unfortunately at the time I added the error handling to other aspects of the scripts, I did not have active Synopsys licenses.

I have updated the scripts now and they are working…[Read more]

Hi Michael,
Sorry I missed your post.

OSVVM pro scripts are a abstract procedure layer on top of TCL. Hence, you can do anything that TCL does. See the scripts OsvvmLibraries/OsvvmLibraries.pro and OsvvmLibraries/osvvm/osvvm.pro for examples.

Best Regards,
Jim

Hi Steve,
I did some testing with Cadence over the last week. Looks like the 2022.08 updates to memory pkg broke some things. On the dev branch of OSVVM, I moved MemoryPkg_c.vhd back to the 2022.06 version.

It also looks like Cadence is failing the singleton tests in CoveragePkg. I need to try to find root cause as the singleton tests in…[Read more]

Hi Oliver,
> Above all, there is no SystemVHDL as a complement to the SystemVerilog
Renaming Verilog to SystemVerilog is simply marketing. Just asking that question demonstrates the brilliance it.

OSVVM provides VHDL with “SystemVerilog + UVM” verification capabilities including Transaction Level Modeling, Constrained Random, Functional…[Read more]