Activity
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Barry Henderson replied to the topic failure to compile a Scoreboard in Modelsim DE using osvvm 2018.04 in the forum OSVVM 7 years ago
Hi Jim, Many thanks for your answer. My problem is that i have tried every which way to get things to compile and i always get errors.My scoreboard generic package is defined like this now in a seperate design unit (i.e. a VHDL file):library IEEE;use IEEE.STD_LOGIC_1164.ALL;library osvvm;–use osvvm.OsvvmContext;use OSVVM.ScoreboardGenericPkg;use…[Read more]
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Jim Lewis replied to the topic Comparing Two std_logic_vectors in the forum VHDL 7 years ago
Hi Torsten,In the IEEE VHDL-2008, there is only numeric_std_unsigned. There is no “signed” package. Jim
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Jorge Tonfat replied to the topic Correct usage of WriteCovDb and ReadCovDb in the forum OSVVM 7 years, 1 month ago
Hi Jim,I found in the ALDEC documentation how to merge the functional coverage using the acdb edit command.Example:
## Merge functional coverage from TSSPWIP
acdb edit -i "$dsn/src/Unit Test/unittest.acdb" -move -merge instance /unittest/TSSPWIP/TC* /unittest/TSSPWIP/TC3RecvErr
Best regards,Jorge -
Jim Lewis wrote a new post 7 years, 4 months ago
Webinar Taming Testbench Messaging and Error Reporting with OSVVM’s Logs and Alerts.
Thursday April 5, 2018
Printing and error reporting in VHDL are tedious, yet necessary testbench tasks. Fortunately, Open S […] -
Torsten replied to the topic Random seed problem in the forum OSVVM 7 years, 6 months ago
Thanks, I get far better results with your workaround. If we change the seed function, we could look what kind of hash functions are used for dictionary types in languages like python. I assume, they use functions which are not cryptographic secure, but have a good uniform distribution and are very fast. But you are right, with such a change, the…[Read more]
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Jim Lewis replied to the topic Possible bug in AlertLogPkg's Log procedure. in the forum OSVVM 7 years, 6 months ago
Hi Reuven,PathTail is intended to extract a component instance label from a PathName. For the string representation of a variable, signal, constant, or even entity name, you can indeed just use simple_name. I will update PathTail in the next revision so that it does not assume the name ends in a “:” and will return what you were…[Read more]
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Tim Wells replied to the topic Positive Acknowledge in Alerts in the forum OSVVM 7 years, 6 months ago
Hi Jim,I would like positive acknowledge in the Report Status. My end client is doing DO-254 with OSVVM and my company is struggling to integrate the two.Thanks,Tim
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Jim Lewis wrote a new post 7 years, 10 months ago
OSVVM: TrainingOSVVM Training Dates Advanced VHDL Testbenches and Verification – OSVVM+ Boot Camp Like the Webinar? Ready to make Open Source VHDL Verification M […]
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Jim Lewis replied to the topic Cannot compile the library with Modelsim 10.5b in the forum OSVVM 7 years, 10 months ago
I test with QuestaSim 10.5b so if you have the compile order correct, you should be fine.How did you compile it? Did you use the osvvm.do file? See: https://github.com/OSVVM/OSVVM/blob/master/osvvm.doDid you use the directions in the OSVVM_release_notes.pdf? See: https://github.com/OSVVM/OSVVM/blob/master/doc/osvvm_release_notes.pdfI note…[Read more]
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Jim Lewis replied to the topic Limitation using MemoryPkg in the forum OSVVM 7 years, 11 months ago
Hi Eilert,In the 2008 standard it says:An implementation shall choose a representation for all floating-point types except for universal_real that conforms either to IEEE Std 754-1985 or to IEEE Std 854-1987; in either case, a minimum representation size of 64 bits is required for this chosen representation.I think this changed before 2008,…[Read more]
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Eilert Backhus replied to the topic RandomPkg: How to set weight for range in the forum OSVVM 8 years, 1 month ago
Hi Jim,I hoped that there’s some solution using the range notation like you showed:With named association, you can also do the following:
A <= RndA.DistSlv((0=>5, 1 to 14 =>1, 15=>5), A'length) ;
I just didn’t expect it to be so straight simple, since the defined type is self defined. You mentioned integer_vectors somewhere else. Are these…[Read more] -
Jim Lewis replied to the topic Reporting ignored bins in the forum OSVVM 8 years, 1 month ago
Hi Roger,I just did a code review regarding AtLeast. Looking at the code, the AtLeast value is the maximum of the one specified by AddBins (the way I usually show to enter it) and the value specified by GenBin (also specified by a first integer value – but then also requires at least 4 parameters be used). Hence, if you specify both, you may be…[Read more]
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Jim Lewis wrote a new post 8 years, 3 months ago
I am getting ready for the next session of Advanced Testbenches and Verification in UK and am looking forward to meeting another group of students.
Ready to improve your VHDL verification methodology? Come join […] -
Jim Lewis replied to the topic Scoreboard Package Error in Questa in the forum OSVVM 8 years, 4 months ago
That unfortunately is a known bug. 10.4 brought some new cool features, but some how broke for the scoreboard in a way that I could not figure out how to work around. If you are just working with the primary releases, the following versions also exhibit the issue: 10.4, 10.4a, 10.4b, 10.4c. 10.3 was fine. 10.4d and 10.5 are fine. The…[Read more]
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Jim Lewis replied to the topic Possible Error in "ScoreboardPkg User Guide.pdf" in the forum OSVVM 8 years, 4 months ago
Good catch. I updated the source document. Thanks.
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Jim Lewis wrote a new post 8 years, 7 months ago
2016.11a is a minor release. The only file that changed is VendorCovApiPkg_Aldec.vhd. There was a bug in one of the attributes that has been fixed and verified.
VendorCovApiPKg simplifies the connection […] -
Mark replied to the topic Problems? Suggestions? in the forum OSVVM 9 years, 5 months ago
When using ReadLogEnables to select what logging is enabled any logs that are enabled descend down the hierarchy. As you can only set not disable logs in a file this means that I can’t enable logging near the top of my hierarchy without this pushing all the way down to the bottom.Would it be possible to change the ReadLogEnables so that it only…[Read more]
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Jim Lewis wrote a new post 9 years, 9 months ago
OSVVM Presentation in Copenhagen
IDA is hosting an OSVVM presentation on 9 November 2015 from 18:30 til 20:30. For details see: http://ida.dk/event/316127
OSVVM and Error Reporting
DVCon Europe in Munich, […] -
Ralf replied to the topic Standard messaging feature in OSVVM? in the forum OSVVM 11 years, 2 months ago
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Steve Chan started the topic PSL or SVA? in the forum VHDL 12 years, 6 months ago
*Hi allI am planning to start embedding the more advance assertion contruct in my HDL/TestBench design.My company is generally a VHDL house, but I can foresee use of SV in the future.A mixed language environment is very likely to happen (as a matter it already exist)I have read either PSL or SVA can work in both SV and VHDL.So which assertion…[Read more]
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