In July, I went to the FPGA Conference Europe. The 2026.08 release has been inspired by presentations I did, presentations done by my colleagues at PLC2 (Patrick and Adrien) and Aldec (Michal), and by hall way discussions. I came back from the FPGA Conference Europe energized and ready. OSVVM release 2026.08 adds the following Updated Requirements Settings Multi-line Alert, Log, LogHeader, PrintLi... »
After 25+ years of SynthWorks VHDL training funding OSVVM development, I am searching for additional sources of funding for OSVVM. Due to AI, I am not confident that training will continue to be able to fund open source development. On GitHub, I have started a sponsors page. If you would like to sponsor OSVVM, go to https://github.com/OSVVM/OsvvmLibraries and click on the Sponsor’s link in t... »
Problem and Solution In 2026.05, if a test case calls SetAxi4Options/GetAxi4Options at time 0 with a parameter other than an AXI4 bus value (such as BRESP) the test case will crash. Problematic use case: ManagerProc : process variable IntOption : integer ; begin -- this process starts at time 0, delta cycle 0 (aka Initialization phase) -- SetAxi4Options or GetAxi4Options access a parameter that is... »
OSVVM release 2026.05 adds the following Script Exit on build done Script Bug Fix: two RunTest when running interactively Script bug: VhdlLsToml Script bug: Simulate and generics Testbench updates to remove Assert WARNING/ERROR from Numeric_Std CoveragePkg Refactor MemoryGenericPkg Support for 64 bit integers AlertLogPkg Use Parent ID DynamicVectorGenericPkg VHDL-2019 Interface Support Ethernet Bu... »
The OSVVM 2026.01 release adds one big feature, PCIe CoSim Verification Component, and numerous smaller updates. PCIe CoSim Verification Component OSVVM now has a co-simulation based PCIe Verification Component thanks to Simon Southwell’s hard work. This reverses the typical co-simulation relationship where software communicates through the MIT interface to an OSVVM VHDL VC. Instead, ... »
The 2025.06 release adds: Build Directories Tcl procedure CreateTestCaseCommonPkg Tcl procedure RunAllTests Questa – new vs. old script flows Clock edge specification for WaitForClock, WaitForTransaction, … Most VC Test Cases updated Build Directories All build output is now collected into a build directory. The default name for is DirName_ScriptName. Set the name with BuildName... »
The 2024 Wilson Verification survey shows that OSVVM is being used by 35% of all FPGA designers world-wide, which makes OSVVM VHDL’s #1 Verification Methodology. Year after year we have made steady gains on UVM (SystemVerilog) in FPGA Verification. In Europe for FPGA, the 2022 survey showed that OSVVM is used more than UVM (38% to 20%). Here are a few reasons why you should be using O... »
I am often asked does OSVVM work in XSIM? With the upcoming OSVVM 2025.02 release – YES!!! As I was wrapping up on OSVVM 2025.02 release, inspired by another instance of this question, I decided to take a look at XSIM 2024.2. »
Recorded Webinars. Why Should Our Team be Using VHDL + OSVVM for Verification? Recording of the session Using OSVVM’s AXI4 Verification Components Part 1 – Creating the AXI4 Testbench (Test Harness) Recording of the session Using OSVVM’s AXI4 Verification Components Part 2 – Writing Tests and Configuring the AXI4 VCs Recording of the session Upcoming OSVVM class sessions.... »
It seems like yesterday that I got back from Verification Futures Conference (June 18) and FPGA Conference Europe (July 2-4) – but it is actually been three weeks now. A big part of that is because as soon as I got back, I have been focused on the OSVVM 2024.07 release – and I tend to get tunnel vision. Verification Futures Conference – June 18 On June 18th I presented Essential ... »