VHDL+OSVVM vs SystemVerilog+UVM
VHDL + Open Source VHDL Verification Methodology (OSVVM) is great for verification and is a competitor to SystemVerilog + UVM. Especially in the FPGA space where VHDL is the dominant language (see the 2020 Wilson Verification Survey). Some refute this claiming that, “VHDL falls flat on its face when used for verification” and “VHDL can do a lot, however, it cannot do everything S... »