2020 was quite a year. While everything else was quite dark, OSVVM had a great 2020. Normally I travel for work around 75K air miles. 2020 none. This saved a lot of time. All of that time (and more) went into enhancing OSVVM. OSVVM had 6 updates in 2020. This includes the 2020.12 revision which was released late on December 31. More on 2020.12 in a future post. Here are some milestones t... »
VHDL-93 (IEEE 1076-1993) created shared variables of an ordinary type as a temporary solution – which was noted in the standard document (aka LRM). VHDL-2000 (IEEE 1076-2000) created protected types as the only type to be used with shared variables and deprecated and removed the usage of a shared variable with an ordinary type. One of the places shared variables of an ordinary type are still use... »
Verification components have become an essential part of a structured VHDL environment. In OSVVM we implement verification components as an entity and architecture. This provides RTL engineers with a familiar environment to create model behavior. The objective of any verification framework is to make the Device Under Test (DUT) “feel like” it has been plugged into the board. Henc... »
OSVVM Model Independent Transactions I take great joy in reuse – this is true whether it is a plastic bag or VHDL code. OSVVM Model Independent Transactions were added in the 2020.07 release and are directed at improving reuse – and hence bring me great joy. Model Independent Transactions provide two aspects of reuse. First, they simplify verification component development by reducing the number... »
It has been a busy summer for OSVVM. With the world working out of home offices, all of our training has shifted to on-line – which fortunately we started doing 7+ years ago. Not having to travel has freed up additional time that I have devoted to OSVVM development. Updates started with adding PASSED counts to the AlertLog data structure in 2020.05. AXI Full verification components (ma... »
INTRODUCTION Most people don’t think of VHDL as a verification language. However, with the Open Source VHDL Verification Methodology (OSVVM) utility and verification component libraries it is. Using OSVVM we can create readable, powerful, and concise VHDL verification environments (testbenches) whose capabilities are similar to other verification languages, such as SystemVerilog and UVM. Thi... »
Up your VHDL verification game with the latest from Open Source VHDL Verification Methodology (OSVVM). OSVVM 2020.07 focuses on Verification Components. AXI4 Full models were added. Axi4Lite, AxiStream, and UART models were updated to use the new OSVVM Model Independent Transactions. AXI4 (and Axi4Lite) verification components are the most challenging and most interesting I have worked on. O... »
Ever wanted to encapsulate all the signals of an interface (such as AXI4Lite, I2C, …) into a single record only to be confounded by not being able to specify the direction for the elements of the record? In this article we will explore how to do this with either VHDL-2019 interfaces or OSVVM interfaces. VHDL-2019 Interfaces Step 1: A Record is the foundation VHDL-2019 interfaces start with a recor... »
In my earlier post I discussed how you could get around the pre-VHDL-2008 scoping rules by using external names, in this post we will look at using an external name to help us write an OSVVM functional coverage model for the Blackjack state machine shown in figure 1: The aim of our functional model is to create a coverage bin for each state transition so we can ensure that during our tests, every ... »
Up your verification game with the latest from Open Source VHDL Verification Methodology (OSVVM). OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC. According to the 2018 Wilson Ve... »